ICS872S480 Datasheet, PDF (8/20 Pages) Integrated Device Technology – Differential-to-HSTL Zero Delay Clock Generator

ICS872S480 Data Sheet
DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Parameter Measurement Information, continued
nCLK[0:1]
nCLK[0:1]
∆t
∆t
nFB_IN
t(Ø)mean
FB_IN
Histogram
Dynamic Phase Offset
➤ t (Ø)
Dynamic Phase Offset =  t(Ø) – t(Ø)_mean
tdyn(Ø) = Peak-to-Peak value of Dynamic Phase Offset Histogram
Where t(Ø) is any random sample, and t(Ø)mean is the average
of the sampled cycles measured on the controlled edges
+V_AC
V_OX
-V_AC
V_OD
V_AC = 150mV for VOUT_SEL = 0
V_AC = 135mV for VOUT_SEL = 1
t_SLEW =
2 * V_AC
∆t
Dynamic Phase Offset
Slew Rate
PLL Lock Time
ICS872S480BK REVISION A APRIL 19, 2011
8
©2011 Integrated Device Technology, Inc.