8413S12I-100 Datasheet, PDF (9/33 Pages) Integrated Device Technology – Ten 100MHz clocks for PCI Express

8413S12I-100 DATA SHEET
Table 7C. AC Characteristics, V_DD = 3.3V ± 5%, V_{DDO_[A:E]} = V_{DDO_F} = V_{DDO_G} = V_{DDO_QREF} = 3.3V ± 5%; or
V_DD = 3.3V ± 5%, V_{DDO_G} = V_{DDO_QREF} = 2.5V ± 5%, T_A = -40°C to 85°C
Symbol Parameter
Output Configurations
Outputs
Minimum Typical Maximum
QA, nQA
3
4
QB, nQB
3
4
R_J
Random Jitter
Q(A:E), nQ(A:E) = 100MHz,
QF = 50MHz,
QG = 125MHz
QREF0 = QREF1 = 25MHz
QC, nQC
QD, nQD
QE, nQE
QA, nQA
QB, nQB
3
4
3
4
3
4
10
40
11
35
D_J
Deterministic Jitter
QC, nQC
QD, nQD
13
42
20
55
QE, nQE
17
42
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Refer to Applications Section for peak-to-peak jitter calculations.
REVISION B 2/03/2015
9
CLOCK GENERATOR FOR CAVIUM PROCESSORS