8413S12I-100 Datasheet, PDF (5/33 Pages) Integrated Device Technology – Ten 100MHz clocks for PCI Express

Function Tables
Table 3A. PLL_SEL Control Input Function Table
Input
PLL_SEL
Operation
0
PLL Bypass
1 (default)
PLL Mode
Table 3B. REF_SEL Control Input Function Table
Input
REF_SEL
Clock Source
0
CLK, nCLK
1 (default)
XTAL_IN,
XTAL_OUT
Table 3C. OE_[A:E] Control Input Function Table
Input
Outputs
OE_[A:E]
Q[Ax:Ex], nQ[Ax:Ex]
0
High-Impedance
1 (default)
Enabled
Table 3D. OE_G Control Input Function Table
Input
Outputs
OE_G
QG
0
High-Impedance
1 (default)
Enabled
Table 3E. OE_REF Control Input Function Table
Input
Output
OE_REF
QREF[1:0]
0
High-Impedance
1 (default)
Enabled
8413S12I-100 DATA SHEET
REVISION B 2/03/2015
5
CLOCK GENERATOR FOR CAVIUM PROCESSORS