8413S12I-100 Datasheet, PDF (12/33 Pages) Integrated Device Technology – Ten 100MHz clocks for PCI Express

8413S12I-100 DATA SHEET
Parameter Measurement Information
1.65V±5%
1.65V±5%
V_DD,
V_{DDO_[F:G],}
V_{DDO_QREF VDDA}
GND
SCOPE
Qx
-1.65V±5%
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
3.3V±5%
3.3V±5%
V_DD,
V_{DDO_[A:E]}
V_DDA
2.05V±5%
1.25V±5%
2.05V±5%
V_DD
2
V_{DDO_G,}
V_{DDO_QREF}
V_DDA
GND
SCOPE
Qx
-1.25V±5%
3.3V Core/2.5V LVCMOS Output Load AC Test Circuit
3.3V±5%
3.3V±5%
V_DD,
V_{DDO_[A:E]}
V_DDA
V_DDA
3.3V Core/3.3V HCSL Output Load AC Test Circuit
This load condition is used for I_DD and tjit(Ø) measurements.
3.3V Core/3.3V HCSL Output Load AC Test Circuit
V_DD
nCLK
V
PP
CLK
GND
Cross Points
V
CMR
Differential Input Level
CLOCK GENERATOR FOR CAVIUM PROCESSORS
RMS Phase Jitter
12
REVISION B 2/03/2015