8413S12I-100 Datasheet, PDF (21/33 Pages) Integrated Device Technology – Ten 100MHz clocks for PCI Express

8413S12I-100 DATA SHEET
Schematic Example
Figure 6 (next page) shows an example of 8413S12I-100 application
schematic. In this example, the device is operated at V_DD = V_{DDO_A}
= V_{DDO_B} = V_{DDO_C} = V_{DDO_D} = V_{DDO_E} = V_{DDO_F} = 3.3V and
V_{DDO_QREF} = 3.3V. The 18pF parallel resonant 25MHz crystal is
used. The load capacitance C1 = 22pF and C2 = 10pF are
recommended for frequency accuracy. Depending on the parasitic of
the printed circuit board layout, these values might require a slight
adjustment to optimize the frequency accuracy. Crystals with other
load capacitance specifications can be used. This will require
adjusting C1 and C2. For this device, the crystal load capacitors are
required for proper operation.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 8413S12I-100 provides
separate power supplies to isolate any high switching noise from
coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side. The other components can be on the opposite side of the
PCB. Power supply filter recommendations are a general guideline to
be used for reducing external noise from coupling into the devices.
The filter performance is designed for a wide range of noise
frequencies. This low-pass filter starts to attenuate noise at
approximately 10kHz. If a specific frequency noise component is
known, such as switching power supplies frequencies, it is
recommended that component values be adjusted and if required,
additional filtering be added. Additionally, good general design
practices for power plane voltage stability suggests adding bulk
capacitance in the local area of all devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure that the logic control inputs are
properly set.
REVISION B 2/03/2015
21
CLOCK GENERATOR FOR CAVIUM PROCESSORS