8413S12I-100 Datasheet, PDF (4/33 Pages) Integrated Device Technology – Ten 100MHz clocks for PCI Express

8413S12I-100 DATA SHEET
Number
Name
Type
Description
Continued on next page.
Active LOW Master Reset. When logic LOW, all outputs are reset causing the
62
nMR
Input
Pullup true outputs Qx to go low and the inverted outputs nQx to go high. When logic
HIGH, all outputs are enabled. LVCMOS/LVTTL interface levels.
63
V_{DDO_F}
Power
64
QF
Output
QF output supply pin (LVCMOS/LVTTL). 3.3V supply.
Single-ended output. 3.3V LVCMOS/LVTTL interface levels.
65
V_{DDO_G}
Power
66
QG
Output
QG output supply pins (LVCMOS/LVTTL). 3.3V or 2.5V supply.
Single-ended output. 3.3V or 2.5V LVCMOS/LVTTL interface levels.
67
OE_G
Input
Pullup
Active HIGH output enable for Bank G output. See Table 3D.
LVCMOS/LVTTL interface levels.
68
OE_REF
Input
Pullup
Active HIGH output enable for QREF[0:1] outputs. See Table 3E.
LVCMOS/LVTTL interface levels.
69,
70
QREF0,
QREF1
Output
Single-ended REF outputs. 3.3V or 2.5V LVCMOS/LVTTL interface levels.
71
V_{DDO_QREF}
Power
QREF[0:1] output supply pin (LVCMOS/LVTTL). 3.3V or 2.5V supply.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
C_IN
R_PULLUP
R_PULLDOWN
R_OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output
Impedance
QF, QG,
QREF[0:1]
QG, QREF[0:1]
Test Conditions
V_{DDO_F} = V_{DDO_G} = V_{DDO_QREF} =
3.465V
V_{DDO_QREF}, V_{DDO_G} = 2.625V
Minimum
Typical
2
51
51
15
15
Maximum
Units
pF
k
k


CLOCK GENERATOR FOR CAVIUM PROCESSORS
4
REVISION B 2/03/2015