8413S12I-100 Datasheet, PDF (22/33 Pages) Integrated Device Technology – Ten 100MHz clocks for PCI Express

8413S12I-100 DATA SHEET
Logic Control Input Examples
Set Logic
Set Logic
VDD _{Input to '1'} VDD _{Input to '0'}
VDDO
C10
0.1u
C11
0.1u
VDDO
C3
0.1u
R15 35
QREF1
Zo = 50
LVCMOS
RU1
1K
To Logic
Input
pins
RD1
Not Install
RU2
Not Install
To Logic
Input
pins
RD2
1K
VDDO_QREF
C4
0.1u
U1
VDD
R6 10
C6
10u
C1
22pF
X1
25M₁ H_{8 p} z_F
VDDA
C7
0.1u
FSEL_E1
XTAL_IN
REF_SEL
XTAL_OUT
C2
10pF
1
2 ^GND
3 ^nc
4 ^nc
5 ^nc
6 ^nc
7 ^nc
8 ^nc
9 ^nc
10 ^nc
11 ^nc
12 ^VDDA
13 ^nc
14 ^nc
15 ^XTAL_IN
16 ^XTAL_OUT
17 ^nc
18 ^REF_SEL
GND
VDD
R9
125
VDD
R10
125
C13
0.1u
Zo = 50
Zo = 50
LVPECL Driv er
CLK
nCLK
R13 R14
84
84
8413S12-100
VDD
C5
0.1u
R1 33
QA0
R3 33
nQA0
54
nc ₅₃
VDD ₅₂
IREF ₅₁
OE_D ₅₀
nQD1 ₄₉
QD1 ₄₈
nQD0 ₄₇
QD0 ₄₆
VDDO_D ₄₅
VDDO_C ₄₄
nQC1 ₄₃
QC1 ₄₂
nQC0 ₄₁
QC0 ₄₀
GND ₃₉
OE_C ₃₈
GND ₃₇
nc
R2
475
IREF
OE_D
nQD1
QD1
nQC0
QC0
VDDO
nQC1
QC1
nQC0
QC0
C9
0.1u
C8
0.1u
OE_C
VDD
C12
0.1u
VDDO
C14
0.1u
VDDO
C15
0.1u
Optional
QE1
R7 33
nQE1
R8 33
3.3V
BLM18BB221SN1
1
2
VDD
C16
0.1uF
Ferrite Bead C17
10uF
Zo = 50
+
Zo = 50
-
R4 R5
50 50
Example
for PCI
Express
Add-In Card
HCSL Termination
Example for PCI
Express
Point-to-Point
Connection
Zo = 50
+
Zo = 50
-
R11 R12
50 50
VDD=VDDO_A=VDDO_B=3.3V
VDDO_C= VDDO_D=VDDO_E=3.3V
VDDO_F=VDDO_QREF=3.3V
Figure 6. 8413S12I-100 Schematic Example
3.3V
BLM18BB221SN1
1
2
VDDO
C20
0.1uF
Ferrite Bead C21
10uF
3.3V
BLM18BB221SN1
1
2
VDDO
C18
0.1uF
Ferrite Bead C19
10uF
CLOCK GENERATOR FOR CAVIUM PROCESSORS
22
REVISION B 2/03/2015