TSI340 Datasheet, PDF (83/149 Pages) Integrated Device Technology – This chapter discusses the following topics about the Tsi340

9. Signals and Pinout
83
9.2.2
Secondary Bus Interface Signals
The Secondary PCI Interface signals are described in the following table.
Table 13: Secondary PCI Interface Signals
Signal Name
S_AD[31:0]
S_CBE_b[3:0]
S_PAR
S_FRAME_b
Pin Number
95, 94, 92, 91, 90,
89, 88, 87, 85, 83,
82, 81, 80, 79, 78,
77, 63, 62, 61, 60,
59, 57, 56, 55, 53,
52, 51, 50, 48, 47,
46, 45
86, 76, 66, 54
67
74
Type
Description
TS Secondary PCI interface address/data.
These signals are a multiplexed address and data bus. During the
address phase or phases of a transaction, the initiator drives a
physical address on S_AD[31:0]. During the data phases of a
transaction, the initiator drives write data, or the target drives read
data, on S_AD[31:0]. When the secondary PCI bus is idle, Tsi340
drives S_AD to a valid logic level when its secondary bus grant is
asserted.
TS Secondary PCI interface command/byte enables.
These signals are a multiplexed command field and byte enable field.
During the address phase or phases of a transaction, the initiator
drives the transaction type on S_CBE_b[3:0]. When there are two
address phases, the first address phase carries the dual address
command and the second address phase carries the transaction type.
For both read and write transactions, the initiator drives byte enables
on S_CBE_b[3:0] during the data phases. When the secondary PCI
bus is idle, Tsi340 drives S_CBE_b to a valid logic level when its
secondary bus grant is asserted. S_PAR TS Secondary PCI interface
parity. Signal S_PAR.
TS Secondary PCI interface parity.
Signal S_PAR carries the even parity of the 36 bits of S_AD[31:0] and
S_CBE_b[3:0] for both address and data phases. Signal S_PAR is
driven by the same agent that has driven the address (for address
parity) or the data (for data parity). Signal S_PAR contains valid parity
one cycle after the address is valid (indicated by assertion of
S_FRAME_b), or one cycle after data is valid (indicated by assertion of
S_IRDY_b for write transactions and S_TRDY_b for read
transactions). Signal S_PAR is driven by the device driving read or
write data one cycle after S_AD is driven. Signal S_PAR is tristated
one cycle after the S_AD lines are tristated. Devices receiving data
sample S_PAR as an input in order to check for possible parity errors.
When the secondary PCI bus is idle, the Tsi340 drives S_PAR to a
valid logic level when its secondary bus grant is asserted (one cycle
after the S_AD bus is parked).
STS Secondary PCI interface FRAME#.
Signal S_FRAME_b is driven by the initiator of a transaction to indicate
the beginning and duration of an access on the secondary PCI bus.
Signal S_FRAME_b assertion (falling edge) indicates the beginning of
a PCI transaction. While S_FRAME_b remains asserted, data
transfers can continue. The deassertion of S_FRAME_b indicates the
final data phase requested by the initiator. When the secondary PCI
bus is idle, S_FRAME_b is driven to a deasserted state for one cycle
and then is sustained by an external pull-up resistor.
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Tsi340 User Manual
80E3000_MA001_05