TSI340 Datasheet, PDF (109/149 Pages) Integrated Device Technology – This chapter discusses the following topics about the Tsi340

11. Register Descriptions
109
Bit
Name
Description
5
VGA snoop enable Controls Tsi340’s response to VGA compatible palette write
transactions. VGA palette write transactions correspond to I/O
transactions whose address bits are as follows:
• P_AD<9:0> are equal to 3C6h, 3C8h, and 3C9h.
• P_AD<15:10> are not decoded.
• P_AD<31:16> must be 0.
0 = VGA palette write transactions on the primary interface
are ignored unless they fall inside Tsi340’s I/O address range.
1 = VGA palette write transactions on the primary interface
are positively decoded and forwarded to the secondary
interface.
6 Parity error response Controls Tsi340’s response when a parity error is detected on
the primary interface.
0 = Tsi340 does not assert P_PERR_b, nor does it set the
data parity reported bit in the status register. Tsi340 does not
report address parity errors by asserting P_SERR_b.
1 = Tsi340 drives P_PERR_b and
conditionally sets the data parity reported bit in the status
register when a data parity error is detected. Tsi340 allows
P_SERR_b assertion when address parity errors are detected
on the primary interface.
7
Wait cycle control Reads as 0 to indicate that Tsi340 does not perform address
or data stepping.
8
SERR# enable
Controls the enable for P_SERR_b on the primary interface.
0 = Signal P_SERR_b cannot be driven by Tsi340.
1 = Signal P_SERR_b can be driven low by Tsi340.
9
Fast back-to-back Reads as 0 to indicate that Tsi340 does not generate fast
enable
back-to-back transactions on the primary bus.
15:10
Reserved
Reserved. Returns 0 when read.
Type
R/W
R/W
R
R/W
R
R
Reset Value
0x0
0x0
0x0
0x0
0x0
0x0
Integrated Device Technology
www.idt.com
Tsi340 User Manual
80E3000_MA001_05