TSI340 Datasheet, PDF (104/149 Pages) Integrated Device Technology – This chapter discusses the following topics about the Tsi340

104
Table 24: Register Map (Continued)
Offset
0x24
Name
Prefetchable Memory Limit
0x24
Prefetchable Memory Base
0x28
0x2C
0x30
Prefetchable Memory Base
Upper 32 Bits
Prefetchable Memory Limit
Upper 32 Bits
I/O Limit Upper 16 Bits
0x30
I/O Base Upper 16 Bits
0x34
0x34
0x38
0x3C
0x3C
0x3C
0x40
0x40
Reserved
ECP Pointer
Reserved
Bridge Control
Interrupt Pin
Interrupt Line
Subsystem ID
Subsystem Vendor ID
0x44
0x44
Arbiter Control
Diagnostic Control
0x44
Chip Control
0x48
0x48
Reserved
Memory Read Control
0x4C
0x4C
0x50-0x60
Secondary Bus Arbiter
Preemption Control
Reserved
Reserved
Bits
31:16
15:0
31:0
31:0
31:16
15:0
-
7:0
-
31:16
15:8
7:0
31:16
15:0
31:16
15:8
7:0
-
7:0
31:24
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11. Register Descriptions
See
“Prefetchable Memory Limit Address Register—Offset
0x24” on page 118
“ Prefetchable Memory Base Address Register—Offset
0x24” on page 118
“ Prefetchable Memory Base Address Upper 32 Bits
Register—Offset 0x28” on page 119
“Prefetchable Memory Limit Address Upper 32 Bits
Register—Offset 0x2C” on page 119
“I/O Limit Address Upper 16 Bits Register—Offset 0x30” on
page 120
“I/O Base Address Upper 16 Bits Register—Offset 0x30”
on page 120
-
“ECP Pointer Register—Offset 0x34” on page 121
-
“Bridge Control Register—Offset 0x3C” on page 122
“Interrupt Pin Register—Offset 0x3C” on page 121
“Interrupt Line Register – Offset 0x3C” on page 121
“Subsystem ID Register — Offset 0x40 ” on page 125
“Subsystem Vendor ID Register — Offset 0x40 ” on
page 125
“Arbiter Control Register—Offset 0x44” on page 127
“Chip Control Register/Diagnostic Control — Offset 0x44”
on page 126
“Chip Control Register/Diagnostic Control — Offset 0x44”
on page 126
-
“Memory Read Control Register — Offset 0x48” on
page 128
“Secondary Bus Arbiter Preemption Control Register —
Offset 0x4C” on page 129
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Tsi340 User Manual
80E3000_MA001_05
Integrated Device Technology
www.idt.com