TSI340 Datasheet, PDF (75/149 Pages) Integrated Device Technology – This chapter discusses the following topics about the Tsi340

75
8. Reset, Clock, and Initialization
This chapter discusses the following topics about the Tsi340:
• “Clocking” on page 75
• “Reset” on page 76
8.1
8.1.1
8.1.2
8.1.3
Clocking
The Tsi340 has a primary and secondary clock. The Tsi340 is a synchronous device in the sense that the
Secondary Clock Outputs are synchronous to the Primary Clock input.
Primary Input
The Primary Clock Input (P_CLK) drives the primary interface. P_CLK can operate between 0 MHz
and 66 MHz.
Secondary Clock Outputs
Tsi340 has four secondary clock outputs, S_CLK_0[3:0], that can be used as clock inputs for up to four
external secondary bus devices.
The S_CLK_0 outputs are derived from P_CLK (that is, they are synchronous to the primary clock).
When both Tsi340 PCI interfaces operate at 66MHz, the Tsi340 secondary clock outputs are identical
in phase to the primary clock input (P_CLK).
The following rules should be followed regarding the secondary output clocks:
• Each secondary clock output is limited to one load.
• Unused secondary clocks should be disabled through software by writing to the “Secondary Clock
Control Register—Offset 0x68” on page 131.
Clock Run
The Tsi340 supports the PCI clock run protocol defined in the PCI Mobile Design Guide 1.0. The
P_CLKRUN_b signal is high when the system's central resource initiates to stop the primary clock
(P_CLK). The Tsi340 then signals that it allows the PCI clock to be stopped by keeping P_CLKRUN#
high, or it will initiate P_CLK to remain running by driving P_CLKRUN_b low for two clocks. After
the two clocks have elapsed, the system’s central resource will keep P_CLKRUN_b low.
There are three conditions where the bridge will keep the primary clock running:
• Bit [26] offset 6Ch is set to 1
• There is a pending transaction running through the bridge
• A secondary device requires the clock
Integrated Device Technology
www.idt.com
Tsi340 User Manual
80E3000_MA001_05