TSI340 Datasheet, PDF (54/149 Pages) Integrated Device Technology – This chapter discusses the following topics about the Tsi340

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3. Address Decoding
The VGA I/O addresses consist of the following I/O addresses:
• 0x3B0 – 0x3BB
• 0x3C0 – 0x3DF
These I/O addresses are aliased every 1 kB throughout the first 64 kB of I/O space. This means that
address bits <15:10> are not decoded and can be any value, while address bits <31:16> must be all
zero.
VGA BIOS addresses starting at 0xC0000 are not decoded in VGA mode.
3.5.2
VGA Snoop Mode
Tsi340 provides VGA snoop mode, allowing for VGA palette write transactions to be forwarded
downstream. This mode is used when a graphics device downstream from Tsi340 needs to snoop or
respond to VGA palette write transactions. To enable the mode, set the VGA snoop bit in the command
register in configuration space (see “Primary Command Register—Offset 0x04” on page 108).
Tsi340 claims VGA palette write transactions by asserting DEVSEL_b in VGA snoop mode.
When the VGA snoop bit is set, Tsi340 forwards downstream transactions with the following I/O
addresses:
• 0x3C6
• 0x3C8
• 0x3C9
These addresses are also forwarded as part of the VGA compatibility mode previously
described. Again, address bits <15:10> are not decoded, while address bits <31:16> must be
equal to 0, which means that these addresses are aliased every 1 KB throughout the first
64 KB of I/O space.
If both the VGA mode bit and the VGA snoop bit are set, Tsi340 behaves in the same way as if only the
VGA mode bit were set.
Tsi340 User Manual
80E3000_MA001_05
Integrated Device Technology
www.idt.com