TSI340 Datasheet, PDF (26/149 Pages) Integrated Device Technology – This chapter discusses the following topics about the Tsi340

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2. PCI Interface
2.2.4
2.2.4.1
Data Phase Transactions
The address phase or phases of a PCI transaction are followed by one or more data phases. A data
phase is completed when IRDY# and either TRDY# or STOP# are asserted. A transfer of data occurs
only when both IRDY# and TRDY# are asserted during the same PCI clock cycle. The last data phase
of a transaction is indicated when FRAME# is deasserted and both TRDY# and IRDY# are asserted, or
when IRDY# and STOP# are asserted.
Depending on the command type, Tsi340 can support multiple data phase PCI transactions.
Write Transactions
Write transactions are treated as either posted write or delayed write transactions.
Posted Write Transactions
Posted write forwarding is used for memory write and for memory write and invalidate transactions.
When Tsi340 determines that a memory write transaction is to be forwarded across the bridge, Tsi340
asserts DEVSEL# with medium timing and TRDY# in the next cycle, provided that enough buffer
space is available in the posted data queue for the address and at least 8 words of data. This enables
Tsi340 to accept write data without obtaining access to the target bus. Tsi340 can accept one Dword of
write data every PCI clock cycle; that is, no target wait states are inserted. This write data is stored in
internal posted write buffers and is subsequently delivered to the target.
Tsi340 continues to accept write data until one of the following events occurs:
• The initiator terminates the transaction by deasserting FRAME# and IRDY#
• An internal write address boundary is reached, such as a cache line boundary or an aligned 4 KB
boundary, depending on the transaction type
• The posted write data buffer is full
When one of the last two events occurs, Tsi340 returns a target disconnect to the requesting initiator on
this data phase to terminate the transaction. Once the posted write data moves to the head of the posted
data queue, Tsi340 asserts its request on the target bus. This can occur while the Tsi340 is still receiving
data on the initiator bus. When the grant for the target bus is received and the target bus is detected in
the idle condition, Tsi340 asserts FRAME# and drives the stored write address out on the target bus.
On the following cycle, Tsi340 drives the first Dword of write data and continues to transfer write data
until all write data corresponding to that transaction is delivered, or until a target termination is
received. As long as write data exists in the queue, Tsi340 can drive 1 Dword of write data each PCI
clock cycle.
Tsi340 ends the transaction on the target bus when one of the following conditions is met:
• All posted write data has been delivered to the target
• The target returns a target disconnect or target retry (Tsi340 starts another transaction to deliver the
rest of the write data)
• The target returns a target abort (Tsi340 discards remaining write data).
• The master latency timer expires, and Tsi340 no longer has the target bus grant (Tsi340 starts
another transaction to deliver remaining write data).
Tsi340 User Manual
80E3000_MA001_05
Integrated Device Technology
www.idt.com