TSI340 Datasheet, PDF (77/149 Pages) Integrated Device Technology – This chapter discusses the following topics about the Tsi340

8. Reset, Clock, and Initialization
77
8.2.3
Chip Reset
The chip reset bit in the Chip Control/Diagnostic register can be used to reset Tsi340 and the secondary
bus. During chip reset, Tsi340 is inaccessible.
When the chip reset bit is set, the entire Tsi340 is reset and all signals are tristated. In addition,
S_RST_b is asserted, and the secondary reset bit is automatically set. The S_RST_b signal remains
asserted until a configuration write operation clears the secondary reset bit.
As soon as chip reset completes, within 20 PCI clock cycles after completion of the configuration write
operation that sets the chip reset bit, the chip reset bit automatically clears and the chip is ready for
configuration.
Integrated Device Technology
www.idt.com
Tsi340 User Manual
80E3000_MA001_05