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| ICS849S625I Datasheet, PDF (7/24 Pages) Integrated Device Technology – Ten selectable differential LVPECL or LVDS outputs | |||
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ICS849S625I Data Sheet
CRYSTAL-TO-LVPECL/LVDS CLOCK SYNTHESIZER
AC Electrical Characteristics
Table 5A. LVPECL AC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Qx = ÷1
575
625
fOUT
Output Frequency
Qx = ÷2
Qx = ÷4
287.5
143.75
312.5
156.25
Qx = ÷5
115
125
tjit(Ã)
RMS Phase Jitter (Random);
NOTE 1
156.25MHz, Integration Range:
(1MHz â 20MHz)
156.25MHz, Integration Range:
(12kHz â 20MHz)
0.373
0.694
tjit(cc) Cycle-to-Cycle Jitter; NOTE 2
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
10% to 90%
65
180
47
tLOCK
PLL Lock Time
Maximum
630
315
157.5
126
0.422
Units
MHz
MHz
MHz
MHz
ps
1.04
ps
25
ps
350
ps
53
%
130
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Outputs configured as LVPECL (SEL_OUT = 1).
NOTE 1: Refer to the Phase Noise Plot.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
Table 5B. LVDS AC Characteristics, VCC = VCCO = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Qx = ÷1
575
fOUT
Output Frequency
Qx = ÷2
Qx = ÷4
287.5
143.75
Qx = ÷5
115
tjit(Ã)
RMS Phase Jitter (Random);
NOTE 1
156.25MHz, Integration Range:
(1MHz â 20MHz)
156.25MHz, Integration Range:
(12kHz â 20MHz)
tjit(cc) Cycle-to-Cycle Jitter; NOTE 2
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
10% to 90%
65
47
tLOCK
PLL Lock Time
Typical
625
312.5
156.25
125
0.375
0.712
190
Maximum
630
315
157.5
126
0.413
Units
MHz
MHz
MHz
MHz
ps
1.26
ps
20
ps
350
ps
53
%
130
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Outputs configured as LVDS (SEL_OUT = 0).
NOTE 1: Refer to the Phase Noise Plot.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
ICS849S625BYI REVISION A OCTOBER 1, 2012
7
©2012 Integrated Device Technology, Inc.
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