ICS849S625I Datasheet, PDF (3/24 Pages) Integrated Device Technology – Ten selectable differential LVPECL or LVDS outputs

ICS849S625I Data Sheet
CRYSTAL-TO-LVPECL/LVDS CLOCK SYNTHESIZER
Table 1. Pin Descriptions
Number
1,
2
3, 12, 31, 46
4,
5
Name
XTAL_IN
XTAL_OUT
V_EE
SELC0,
SELC1
6
OEA
7, 48
8
V_CC
OEB
9
10,
11
13, 19, 24,
32, 37
14, 15
16, 17
18
20, 21
22, 23
25, 26
27, 28
29, 30
33, 34
35, 36
38, 39
40
41,
42
43
44
45
47
OEC
SELB0,
SELB1
V_CCO
nQC1, QC1
nQC0, QC0
nc
nQB1, QB1
nQB0, QB0
nQA5, QA5
nQA4, QA4
nQA3, QA3
nQA2, QA2
nQA1, QA1
nQA0, QA0
V_CCA
SELA1,
SELA0
SEL_OUT
MR
BYPASS
REF_CLK
Type
Description
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Power
Input
Input
Power
Input
Input
Input
Pulldown
Pullup
Pullup
Pullup
Pulldown
Negative supply pins.
Selects the output divider value. See Table 3D.
LVCMOS/LVTTL interface levels.
Active high output enable. When logic HIGH, Bank A outputs are enabled and
active. When logic LOW, the outputs are disabled and forced to HIGH/LOW.
LVCMOS/LVTTL interface levels.
Core supply pins.
Active high output enable. When logic HIGH, Bank B outputs are enabled and
active. When logic LOW, the outputs are disabled and forced to HIGH/LOW.
LVCMOS/LVTTL interface levels.
Active high output enable. When logic HIGH, Bank C outputs are enabled and
active. When logic LOW, the outputs are disabled and forced to HIGH/LOW.
LVCMOS/LVTTL interface levels.
Selects the output divider value. See Table 3C.
LVCMOS/LVTTL interface levels.
Power
Output supply pins.
Output
Output
Unused
Output
Output
Output
Output
Output
Output
Output
Output
Power
Input
Input
Input
Input
Input
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Differential output pair. LVPECL or LVDS interface levels.
Differential output pair. LVPECL or LVDS interface levels.
No connect.
Differential output pair. LVPECL or LVDS interface levels.
Differential output pair. LVPECL or LVDS interface levels.
Differential output pair. LVPECL or LVDS interface levels.
Differential output pair. LVPECL or LVDS interface levels.
Differential output pair. LVPECL or LVDS interface levels.
Differential output pair. LVPECL or LVDS interface levels.
Differential output pair. LVPECL or LVDS interface levels.
Differential output pair. LVPECL or LVDS interface levels.
Analog supply pin.
Selects the output divider value. See Table 3B.
LVCMOS/LVTTL interface levels.
Selects between either LVDS or LVPECL output levels. See Table 3A.
LVCMOS/LVTTL interface levels.
Master Reset. LVCMOS/LVTTL interface levels.
PLL BYPASS mode select pin. See Table 3F.
LVCMOS/LVTTL interface levels.
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulludown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
ICS849S625BYI REVISION A OCTOBER 1, 2012
3
©2012 Integrated Device Technology, Inc.