ICS849S625I Datasheet, PDF (10/24 Pages) Integrated Device Technology – Ten selectable differential LVPECL or LVDS outputs

ICS849S625I Data Sheet
Parameter Measurement Information
2V
2V
V_CC,
V_CCO
V_CCA
SCOPE
Qx
nQx
V_EE
-1.3V±0.165V
LVPECL Output Load AC Test Circuit
CRYSTAL-TO-LVPECL/LVDS CLOCK SYNTHESIZER
3.3V±5%
POWER SUPPLY
+ Float GND –
V_CC,
V_CCO
V_CCA
SCOPE
Qx
nQx
LVDS Output Load AC Test Circuit
Phase Noise Plot
RMS Phase Jitter =
f₁ ^{Offset Frequency} f₂
1
2*
*
*ƒ
Area Under Curve Defined by the Offset Frequency Markers
RMS Phase Jitter
nQAx,
nQBx,
nQCx
QAx,
QBx,
QCx
tcycle n
➤
tcycle n+1
➤
| | t^{jit(cc) =} t^{cycle n –} t^{cycle n+1}
1000 Cycles
Cycle-to-Cycle Jitter
nQAx,
nQBx,
nQCx
QAx,
QBx,
QCx
10%
90%
t_R
90%
t_F
V_{SW I N G}
10%
nQAx,
nQBx,
nQCx
QAx,
QBx,
QCx
10%
90%
t_R
90%
t_F
V_OD
10%
LVPECL Output Rise/Fall Time
LVDS Output Rise/Fall Time
ICS849S625BYI REVISION A OCTOBER 1, 2012
10
©2012 Integrated Device Technology, Inc.