ICS849S625I Datasheet, PDF (19/24 Pages) Integrated Device Technology – Ten selectable differential LVPECL or LVDS outputs

ICS849S625I Data Sheet
CRYSTAL-TO-LVPECL/LVDS CLOCK SYNTHESIZER
LVDS Power Considerations
This section provides information on power dissipation and junction temperature for the ICS849S625I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS849S625I is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for V_CC = 3.3V + 5% = 3.465V, which gives worst case results.
The maximum current at 85°C is as follows:
I_{CC_MAX} = 100mA
I_{CCA_MAX} = 15mA
I_{CCO_MAX} = 212mA
• Power (core)_MAX = V_{CC_MAX} * (I_{CC_MAX} + I_{CCA_MAX}) = 3.465V * (100mA + 15mA) = 398.475mW
• Power (outputs)_MAX = V_{CCO_MAX} * I_{CCO_MAX} = 3.465V * 212mA = 734.58mW
Total Power__MAX = 398.475mW + 734.58mW = 1133.1mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = _JA * Pd_total + T_A
Tj = Junction Temperature
_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 33.1°C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.133W * 33.1°C/W = 122.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 8. Thermal Resistance _JA for 48 Lead TQFP, E-Pad, Forced Convection
_JA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
33.1°C/W
1
27.2°C/W
2.5
25.7°C/W
ICS849S625BYI REVISION A OCTOBER 1, 2012
19
©2012 Integrated Device Technology, Inc.