ICS849S625I Datasheet, PDF (16/24 Pages) Integrated Device Technology – Ten selectable differential LVPECL or LVDS outputs

ICS849S625I Data Sheet
CRYSTAL-TO-LVPECL/LVDS CLOCK SYNTHESIZER
Application Schematic Example
Figure 5 shows an example of ICS849S625I application schematic. In this example, the device is operated at V_CC = V_CCA = V_CCO = 3.3V. An
18pF parallel resonant 25MHz crystal is used. The load capacitance C1 = 27pF and C2 = 27pF are recommended for frequency accuracy.
Depending on the parasitics of the printed circuit board layout, these values might required slight adjustment to optimize the frequency
accuracy. Crystals with other load capacitance specifications can be used. This will require adjusting C1 and C2. For this device, the crystal
load capacitors are required for proper operation.
As with any high speed analog circuitry, the power supply pins are vulnerable to noise. To achieve optimum jitter performance, power supply
isolation is required. The ICS849S625I provides separate power supplies to isolate from coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB
as close to the power pins as possible. If space is limited, the 0.1uF capacitor in each power pin filter should be placed on the device side of
the PCB and the other components can be placed on the opposite side.
Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter
performance is designed for wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific
frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be adjusted and
if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk
capacitances in the local area of all devices.
The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables
in the datasheet to ensure the logic control inputs are properly set.
VCC O
VCC
VCC
C1
0.01u
C2
0. 01u
C3
0.01u
C4
0.01u
C5
0. 01u
C6
0.01u
C7
0.01u
R 2 10
VCC A
C 11
10uF
C 10
0. 01u
U1
Tuning
capacitor
required
X1
C1
27pF
S E LA0
S E LA1
S E LB0
S E LB1
SELC0
SELC1
O EA
O EB
O EC
41
42 SELA0
S E LA1
10
11 ^SELB0
S E LB1
4
5 ^SELC0
SELC1
6
8 ^{O EA}
9 ^{O EB}
O EC
CL =1 8p F
25MHz
1
XTA L_IN
2
XTAL_OU T
39
QA0 38
nQA0 36
QA1 35
nQA1 34
QA2 33
nQA2 30
QA3 ₂₉
nQA3 ₂₈
QA4 ₂₇
nQA4 ₂₆
QA5 ₂₅
nQ A5
23
QB0 ₂₂
nQB0 ₂₁
QB1 ₂₀
nQ B1
17
QC 0 ₁₆
nQC 0 ₁₅
QC 1 ₁₄
nQC 1
QA0
nQ A
QA1
nQ A1
QA2
nQ A2
QA3
nQ A3
QA4
nQ A4
QA5
nQ A5
QB0
nQ B0
QB1
nQ B1
Q C0
nQ C0
Q C1
nQ C1
C2
27pF
I CS849S625I
SEL_O UT
nR ESET
PLL_BY PASS
R7 1K
Logic Control Input Examples
Set Logic
Set Logic
VC C _{Input to '1'} VCC _{Input to '0'}
R U1
1K
R U2
N ot Install
3.3V
BLM18BB221SN 1
1
2
Fer rite Bead C13
C 12
0. 1uF
VCC
C14
10uF
0.1uF
To Logic
Input
pins
R D1
N ot I nstall
To Logic
Input
pins
R D2
1K
3.3V
BLM18BB221SN 2
1
2
VC CO
C 15
0. 1uF
Fer rite Bead
C16
C17
10uF
0.1uF
Z o_dif f = 100 ohm
LVDS
Term in ation
R1
+
100
-
3. 3V
R3
133
Zo = 50 Ohm
R4
133
+
Zo = 50 Ohm
-
LVPECL
R5
R6
Termination ^82.5
82.5
Zo = 50 Ohm
Zo = 50 Ohm
LVPECL
Op ti on al
Y-Term in ati on
+
-
R 8 R9
50 50
R 10
50
Figure 5. ICS849S625I Application Schematic
ICS849S625BYI REVISION A OCTOBER 1, 2012
16
©2012 Integrated Device Technology, Inc.