ICS8402015I Datasheet, PDF (7/19 Pages) Integrated Device Technology – FemtoClock™ Crystal-to-LVDS/LVCMOS Frequency

ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Table 6. AC Characteristics, V_DD = V_{DDO_A} = V_{DDO_B} = V_{DDO_C} = V_{DDO_REF} = 3.3V±5%, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
QA[0:2]
25
QA[0:1]
50
f_out
Output Frequency ^QB[0:2]
125
QC[0:2]/
nQC[0:2]
125
REF_OUT
25
QA0:QA2,
REF_OUT
25MHz, Integration Range:
12kHz - 1MHz
0.642
tjit(Ø)
RMS Phase Noise
Jitter; NOTE 1
QB0:QB2
125MHz, Integration Range:
637kHz - 62.5MHz
0.389
QC0:QC2
125MHz, Integration Range:
637kHz - 62.5MHz
0.373
tsk(b)
Bank Skew;
NOTE 2, 3
QA[0:2], QB[0:2]
QC[0:2]/nQC[0:2]
45
35
t_R / t_F
Output
Rise/Fall Time
QA[0:2], QB[0:2],
REF_OUT
QC[0:2]/
nQC[0:2]
20% to 80%
20% to 80%
0.425
145
1.15
415
odc
Output
Duty Cycle
QA[0:2], QB[0:2],
REF_OUT
QC[0:2]/
nQC[0:2]
48
52
48
52
Units
MHz
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ns
ps
%
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Please refer to Phase Noise Plots.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
ICS8402015AKI REVISION A JUNE 25, 2009
7
©2009 Integrated Device Technology, Inc.