ICS8402015I Datasheet, PDF (14/19 Pages) Integrated Device Technology – FemtoClock™ Crystal-to-LVDS/LVCMOS Frequency

ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Schematic Example
Figure 6 shows an example of ICS8402015I application schematic. In
this example, the device is operated at V_DD = V_{DDO_REF} = V_{DDO_A} =
V_{DDO_B} = V_{DDO_C} = 3.3V. The 18pF parallel resonant 25MHz crystal
is used. The C1 = 27pF and C2 = 27pF are recommended for
frequency accuracy. For different board layouts, the C1 and C2 may
be slightly adjusted for optimizing frequency accuracy. Two example
of LVDS for receiver without built-in termination and one example of
LVCMOS are shown in this schematic.
Logic Input Pin Examples
Set Logic
VDD _{Input to}
'1'
RU1
1K
Set Logic
VDD _{Input to}
'0'
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
VDD
R2 ₁₀
VDDA
C3
0.01uF
C6
10uF
XTAL_IN
18pF
C1
27pF
X1
25MHz
XTAL_OUT
C2
27pF
U1
25
OE0
OE1
OE2
26
27
28
29
30
GND
VDDA
OE0
OE1
OE2
31
32
XTAL_IN
XTAL_OUT
GND
QC2
VDDO
nQC2
Zo = 50 Ohm
QC2
+
R1
Zo = 50 Ohm 100
nQC2
-
QC0
nQC0
VDD
VDD=3.3V
VDDO=3.3V
16
GND
VDD
MR
GND
QB2
15
14
13
12
11
QB1
QB0
VDDO_B
10
9
VDD
MR
QBQ2B2
C4
0.1uF
Zo = 50 Ohm
QC0
R3
50
+
C5
0.1uF
-
R4
Zo = 50 Ohm
50
nQC0
Alternate
LVDS
Termination
VDDO
(U1:1) VDDO (U1:8) (U1:9)
(U1:17) (U1:24)
C7
0.1uF
C8
0.1uF
C9
0.1uF
C10
0.1uF
C11
0.1uF
Figure 6.ICS8402015I Schematic Example
REF_OUT
R5
30 Zo = 50 Ohm
R6
30 Zo = 50 Ohm
LVCMOS
LVCMOS
ICS8402015AKI REVISION A JUNE 25, 2009
14
©2009 Integrated Device Technology, Inc.