ICS8402015I Datasheet, PDF (15/19 Pages) Integrated Device Technology – FemtoClock™ Crystal-to-LVDS/LVCMOS Frequency

ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8402015I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8402015I is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for V_DD = 3.3V + 5% = 3.465V, which gives worst case results.
Core and LVDS Output Power Dissipation
• Power (core, LVDS) = V_{DD_MAX} * (I_DD + I_{DDO_X} + I_DDA) = 3.465V * (30mA + 26mA + 36mA) = 318.78mW
LVCMOS Output Power Dissipation
• Output Impedance R_OUT Power Dissipation due to Loading 50Ω to V_DDO/2
Output Current I_OUT = V_{DDO_MAX} / [2 * (50Ω + R_OUT)] = 3.465V / [2 * (50Ω + 20Ω)] = 24.7mA
• Power Dissipation on the R_OUT per LVCMOS output
Power (R_OUT) = R_OUT * (I_OUT)² = 20Ω * (24.7mA)² = 12.25mW per output
• Total Power Dissipation on the R_OUT
Total Power (R_OUT) = 12.25mW * 6 = 73.5mW
Total Power Dissipation
• Total Power
= Power (core, LVDS) + Total Power (R_OUT)
= 318.78mW + 73.5mW
= 392.28mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The
maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θ_JA * Pd_total + T_A
Tj = Junction Temperature
θ_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 37°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.392W * 37°C/W = 99.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance θ_JA for 32 Lead VFQFN, Forced Convection
θ_JA Vs. Air Flow
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
37.0°C/W
1
32.4°C/W
2.5
29.0°C/W
ICS8402015AKI REVISION A JUNE 25, 2009
15
©2009 Integrated Device Technology, Inc.