ICS8402015I Datasheet, PDF (10/19 Pages) Integrated Device Technology – FemtoClock™ Crystal-to-LVDS/LVCMOS Frequency

ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Parameter Measurement Information, continued
V_DD
DC Input _LVDS
➤
out
I_OS
➤
I_OSB
out
LVDS
➤ ^VDD
I_OFF
Output Short Circuit Current Setup
Power Off Leakage Setup
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS8402015I provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. V_DD, V_DDA, V_{DDO_A,} V_{DDO_B,} V_{DDO_C,} and
V_{DDO_REF} should be individually connected to the power supply
plane through vias, and 0.01µF bypass capacitors should be used for
each pin. Figure 1 illustrates this for a generic V_DD pin and also
shows that V_DDA requires that an additional 10Ω resistor along with
a 10µF bypass capacitor be connected to the V_DDA pin.
3.3V
V_DD
.01µF _10Ω
V_DDA
.01µF
10µF
Figure 1. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
Outputs:
LVDS Outputs
All unused LVDS outputs should be terminated with 100Ω resistor
between the differential pair.
LVCMOS Outputs
All unused LVCMOS output can be left floating. There should be no
trace attached.
ICS8402015AKI REVISION A JUNE 25, 2009
10
©2009 Integrated Device Technology, Inc.