ICS813078I Datasheet, PDF (7/26 Pages) Integrated Device Technology – FEMTOCLOCKS™ VCXO-PLL FREQUENCY GENERATOR FOR WIRELESS INFRASTRUCTURE EQUIPMENT

ICS813078I
FEMTOCLOCKS™ VCXO-PLL FREQUENCY GENERATOR
Table 3I. Reset (nMR) Configuration Table
Input
nMR
Operation
0
The Femto-PLL is reset.
1 (default) Normal operation.
Table 3J. Output Disable (nSTOPA) Configuration Table.
Input
nSTOPA
Operation
0
QA[2:0]/nQA[2:0] outputs are stopped in logic LOW state. The assertion of nSTOPA is asynchronous
to the internal clock signal and may cause an output runt pulse.
1 (default)
Normal operation and outputs enabled.
Table 3K. Output Disable (nSTOPB) Configuration Table.
Input
nSTOPB
Operation
0
QB[1:0] / nQB[1:0] outputs are stopped in logic LOW state. The assertion of nSTOPB is
asynchronous to the internal clock signal and may cause an output runt pulse.
1 (default)
Normal operation and outputs enabled.
Table 3L. Output Disable (nSTOPC) Configuration Table.
Input
nSTOPC
Operation
0
QC[3:0] outputs are stopped in logic LOW state. The assertion of nSTOPC is asynchronous to the
internal clock signal and may cause an output runt pulse.
1 (default)
Normal operation and outputs enabled.
Table 3M. PLL Lock Status Output (LOCK_DT) Configuration Table.
Output
Conditions LOCK_DT
Locked Constantly HIGH.
Unlocked HIGH with occasional LOW pulses.
FEMTOCLOCKS™ VCXO-PLL FREQUENCY GENERATOR
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ICS813078BYI REV. A OCTOBER 6, 2008