ICS813078I Datasheet, PDF (3/26 Pages) Integrated Device Technology – FEMTOCLOCKS™ VCXO-PLL FREQUENCY GENERATOR FOR WIRELESS INFRASTRUCTURE EQUIPMENT

ICS813078I
FEMTOCLOCKS™ VCXO-PLL FREQUENCY GENERATOR
Table 1. Pin Descriptions
Number
1
Name
LF1
2
LF0
3
4, 25, 26,
47, 48, 49
5
6, 7, 37, 61
8
ISET
nc
FLM
V_CC
CLK1
9
REF_SEL
10
nMR
11
CLK0
12
nCLK0
13, 36, 43,
50, 54, 58, 64
V_EE
14. 15
NA1, NA0
16, 17
NB1, NB0
18, 19
NC1, NC0
20, 21, 22 R2, R1, R0
23,
BYPASS1,
24
BYPASS0
27
V_CCA
28
nSTOPA
29
nSTOPB
30
nSTOPC
31, 32
QB1, nQB1
33, 40, 46
34, 35
V_CCO
QB0, nQB0
38, 39
QA2, nQA2
41, 42
QA1, nQA1
44, 45
QA0, nQA0
continued on next page.
Type
Analog
Input
Analog
Output
Analog
Description
Input from external loop filter. VCXO control voltage input.
Output to external loop filter. Charge pump output.
Charge pump current-settings pin.
Unused
No connect.
Input
Power
Input
Input
Input
Input
Input
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
Pullup/
Pulldown
VCXO-PLL fast lock mode. See Table 3H. LVCMOS/LVTTL interface levels.
Power supply pins for LVPECL outputs.
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Selects the input reference clock. See Table 3F.
LVCMOS/LVTTL interface levels.
Master reset. See Table 3I. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Power
Negative supply pins.
Input
Input
Input
Input
Pulldown
Pulldown
Pulldown
Pulldown
Femto-PLL output-divider for QAn/nQAn outputs. See Table 3B.
LVCMOS/LVTTL interface levels.
Femto-PLL output-divider for QBn/nQBn outputs. See Table 3C.
LVCMOS/LVTTL interface levels.
Femto-PLL output-divider for QCn outputs. See Table 3D.
LVCMOS/LVTTL interface levels.
VCXO-PLL pre-divider and VCXO multiplier selection. See Table 3A.
LVCMOS/LVTTL interface levels.
Input
Pullup PLL mode selections. See Table 3G. LVCMOS/LVTTL interface levels.
Power
Input
Input
Input
Output
Power
Output
Output
Output
Output
Pullup
Pullup
Pullup
Analog supply pin.
Output clock stop for Bank A. See Table 3J. LVCMOS/LVTTL interface levels.
Output clock stop for Bank B. See Table 3K. LVCMOS/LVTTL interface levels.
Output clock stop for Bank C. See Table 3L. LVCMOS/LVTTL interface levels.
Bank B output pair. LVPECL interface levels.
Output supply pins for LVPECL outputs.
Bank B output pair. LVPECL interface levels.
Differential Bank A output pair. LVPECL interface levels.
Differential Bank A output pair. LVPECL interface levels.
Differential Bank A output pair. LVPECL interface levels.
FEMTOCLOCKS™ VCXO-PLL FREQUENCY GENERATOR
3
ICS813078BYI REV. A OCTOBER 6, 2008