ICS813078I Datasheet, PDF (6/26 Pages) Integrated Device Technology – FEMTOCLOCKS™ VCXO-PLL FREQUENCY GENERATOR FOR WIRELESS INFRASTRUCTURE EQUIPMENT

ICS813078I
FEMTOCLOCKS™ VCXO-PLL FREQUENCY GENERATOR
Table 3F. Input Reference Clock Multiplexer (REF_SEL) Configuration Table
Input
REF_SEL Operation
0 (default) Selects CLK0, nCLK0 differential input pair as reference frequency.
1
Selects CLK1 single-ended input as reference frequency.
The input reference selector should be tied to logic 0, selecting the differential clock inputs, for best signal integrity and lowest phase noise
Table 3G. PLL Bypass (BYPASS) Configuration Table
Input
BYPASS1
BYPASS0 Operation
0
X
f_OUT = ((f_REF ÷ P) * MV * MF) ÷ NA, NB, or NC.
VCXO-PLL operation, jitter attenuation and frequency multiplication enabled.
f_OUT = ((f_REF ÷ P) * MV) ÷ NA, NB, or NC.
1
0
VCXO-PLL enabled, Femto-PLL bypassed. Jitter attenuation (VCXO-PLL) enabled.
AC specifications do not apply.
1 (default)
1 (default)
f_OUT = f_REF ÷ NA, NB, or NC.
VCXO-PLL and Femto-PLL bypassed, no jitter attenuation and frequency multiplication.
AC specifications do not apply.
The BYPASS[1:0] controls should be set to logic LOW level for normal operation. BYPASS = 1x enables the PLL bypass mode for factory
test. In PLL Bypass Mode, the output frequency is divided by NA, NB, or NC dividers.
Table 3H. Fast Lock Mode (FLM) Configuration Table
Input
FLM
Operation
0 (default) Normal operation.
1
Fast PLL lock operation. Use this mode only during startup to decrease PLL lock time.
V_CC = 3.3V
0V
t_LOCK
LOCK
VCXO-PLL Acquires Lock
VCXO-PLL Locked
FLM
Fast Lock Mode
(High VCXO-PLL Bandwidth)
Nominal VCXO-PLL Bandwidth
Figure 1. Recommended Start-up Timing Diagram
FEMTOCLOCKS™ VCXO-PLL FREQUENCY GENERATOR
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ICS813078BYI REV. A OCTOBER 6, 2008