ICS813078I Datasheet, PDF (4/26 Pages) Integrated Device Technology – FEMTOCLOCKS™ VCXO-PLL FREQUENCY GENERATOR FOR WIRELESS INFRASTRUCTURE EQUIPMENT

ICS813078I
FEMTOCLOCKS™ VCXO-PLL FREQUENCY GENERATOR
Number
51, 53, 55, 57
52, 56
59
Name
QC3, QC2,
QC1, QC0
V_{CCO_CMOS}
LOCK
60
MF
62, 63
XTAL_OUT,
XTAL_IN
Type
Description
Output
Single-ended Bank C outputs. LVCMOS/LVTTL interface levels.
Power
Output
Input
Input
Pulldown
Output supply pins for LVCMOS outputs.
VCXO lock state. LVCMOS/LVTTL interface levels. See Table 3M.
FemtoClock-PLL feedback divider selection. See Table 3E.
LVCMOS/LVTTL interface levels.
Internal VCXO crystal oscillator interface.
XTAL_IN is the input. XTAL_OUT is the output.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol Parameter
C_IN
Input Capacitance
C_PD
Power Dissipation
Capacitance (per output)
R_PULLUP Input Pullup Resistor
R_PULLDOWN Input Pulldown Resistor
R_OUT
Output Impedance QC[3:0]
Test Conditions
V_CC = V_{CCO_CMOS} = 3.465V
Minimum
Typical
4
Maximum
Units
pF
10
pF
51
kΩ
51
kΩ
15
Ω
D C EVICE ONFIGURATION
The ICS813078I is a two stage device, a VCXO-PLL stage
followed by a low phase noise FemtoClock PLL multiplier stage.
The VCXO-PLL stage uses a pullable crystal to lock to the
reference clock. The low phase noise FemtoClock multiplies the
VCXO-PLL output clock up to 491.52MHz or 614.4MHz and three
independent output dividers scale the frequency down to the
desired output frequencies. With a given input and VCXO
frequency, the output frequency is a function of the P, MF, MV and
the NA, NB and NC dividers. The P and MV are controlled by the
R[2:0] control pins through the internal lookup table (LUT).
The VCXO-PLL pre-divider (P) down-scales the input reference
frequency f_REF and enables the use of the ICS813078I at a variety
of input frequencies. P and MV must be set to match the VCXO
frequency: f_REF ÷ P = f_VCXO ÷ MV. For example, at the nominal
VCXO frequency of 30.72MHz and if MV equals one, the input
frequency must be an integer multiple of 30.72MHz (for MV = 2, the
input frequency must be an integer multiple of 15.36MHz). The
FemtoClock PLL stage multiplies the VCXO frequency (30.72MHz)
to 614.4MHz or 491.52MHz by a multiplier MF of 20 or 16. The
output frequency equals [(f_REF ÷ P) * MV * MF] ÷ NA, NB, or NC.
The NA, NB and NC dividers operate independently.
Table 3A. Input Frequency Configuration Example
Table (fVCXO = 30.72MHz)
fref
(MHz)
Input
R[2:0]
Internal Dividers
P
MV
fXTAL
(MHz)
30.72
000
1
1
30.72
61.44
001
2
1
30.72
122.88
010
4
1
30.72
15.36
011
1
2
30.72
10
100
125
384
30.72
12.8
101
5
12
30.72
15
110
125
256
30.72
20
111
125
192
30.72
FEMTOCLOCKS™ VCXO-PLL FREQUENCY GENERATOR
4
ICS813078BYI REV. A OCTOBER 6, 2008