ICS813078I Datasheet, PDF (5/26 Pages) Integrated Device Technology – FEMTOCLOCKS™ VCXO-PLL FREQUENCY GENERATOR FOR WIRELESS INFRASTRUCTURE EQUIPMENT

ICS813078I
FEMTOCLOCKS™ VCXO-PLL FREQUENCY GENERATOR
Table 3B. PLL Output-Divider (NA) Configuration Table.
Inputs
NA1
NA0
0 (default) 0 (default)
0
1
1
0
1
1
Output-Divider
NA
Operation
2
f_QAn = f_VCO ÷ 2
4
f_QAn = f_VCO ÷ 4
5
f_QAn = f_VCO ÷ 5
8
f_QAn = f_VCO ÷ 8
QAn Output
Frequency (MHz)
MF = 0 MF = 1
245.76
307.2
122.88
153.6
98.304
122.88
61.44
76.8
Table 3C. PLL Output-Divider (NB) Configuration Table.
Inputs
NB1
NB0
0 (default) 0 (default)
0
1
1
0
1
1
Output-Divider
NB
Operation
1
f_QBn = f_VCO ÷ 1
4
f_QBn = f_VCO ÷ 4
5
f_QBn = f_VCO ÷ 5
8
f_QBn = f_VCO ÷ 8
QBn Output
Frequency (MHz)
MF = 0 MF = 1
491.52
614.4
122.88
153.6
98.304
122.88
61.44
76.8
Table 3D. PLL Output-Divider (NC) Configuration Table.
Inputs
NC1
NC0
0 (default) 0 (default)
0
1
1
0
1
1
Output-Divider
NC
Operation
4
f_QCn = f_VCO ÷ 4
5
f_QCn = f_VCO ÷ 5
8
f_QCn = f_VCO ÷ 8
16
f_QCn = f_VCO ÷ 16
QCn Output
Frequency (MHz)
MF = 0 MF = 1
122.08
153.6
98.304
122.88
61.44
76.8
30.72
38.4
Table 3E. Femtoclock PLL Feedback Divider (MF) Configuration Table (f_XTAL = 30.72MHz)
Input
MF
Feedback Divider MF Operation
0 (default)
1
16
f_VCO = f_VCXO x 16 = 491.52MHz
20
f_VCO = f_VCXO x 20 = 614.4MHz
FEMTOCLOCKS™ VCXO-PLL FREQUENCY GENERATOR
5
ICS813078BYI REV. A OCTOBER 6, 2008