ICS813078I Datasheet, PDF (17/26 Pages) Integrated Device Technology – FEMTOCLOCKS™ VCXO-PLL FREQUENCY GENERATOR FOR WIRELESS INFRASTRUCTURE EQUIPMENT

ICS813078I
FEMTOCLOCKS™ VCXO-PLL FREQUENCY GENERATOR
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V_CC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V_CC = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
Single Ended Clock Input
V_REF
C1
0.1u
VCC
R1
1K
CLK
nCLK
R2
1K
Figure 2. Single-Ended Signal Driving Differential Input
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter
performance, power supply isolation is required. The ICS813078I
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V_CC, V_CCA, V_CCO and
V_{CCO_CMOS} should be individually connected to the power supply
plane through vias, and 0.01µF bypass capacitors should be used
for each pin. Figure 3 illustrates this for a generic V_CC pin and also
shows that V_CCA requires that an additional 10Ω resistor along with
a 10µF bypass capacitor be connected to the V_CCA pin.
3.3V
VCC
.01µF _10Ω
V_CCA
.01µF
10µF
Figure 3. Power Supply Filtering
FEMTOCLOCKS™ VCXO-PLL FREQUENCY GENERATOR
17
ICS813078BYI REV. A OCTOBER 6, 2008