9DBV0441 Datasheet, PDF (7/17 Pages) Integrated Circuit Systems – 53mW typical power consumption in PLL mode

9DBV0441 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = T_COM or T_IND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
1.8V Supply Voltage
VDD
Supply voltage for core, analog and LVCMOS
1.7
1.8
1.9
V
1
outputs
Ambient Operating
T_COM
Commmercial range
0
25
70
°C
1
Temperature
T_IND
Industrial range
-40
25
85
°C
1
Input High Voltage
V_IH
Single-ended inputs, except SMBus
0.75 V_DD
V_DD + 0.3 V
1
Input Mid Voltage
V_IM
Single-ended tri-level inputs ('_tri' suffix)
0.4 V_DD
0.6 V_DD
V
1
Input Low Voltage
V_IL
Single-ended inputs, except SMBus
-0.3
0.25 V_DD V
1
Input Current
I_IN
Single-ended inputs, V_IN = GND, V_IN = VDD
-5
Single-ended inputs
I_INP
V_IN = 0 V; Inputs with internal pull-up resistors
-200
V_IN = VDD; Inputs with internal pull-down resistors
5
uA
1
200
uA
1
F_ibyp
Bypass mode
1
200
MHz
2
Input Frequency
F_ipll100
F_ipll125
100MHz PLL mode
125MHz PLL mode
50
100.00 140
MHz
2
62.5 125.00 175
MHz
2
F_ipll62
50MHz PLL mode
25
50.00
65
MHz
2
Pin Inductance
L_pin
7
nH
1
C_IN
Logic Inputs, except DIF_IN
1.5
Capacitance
C_{INDIF_IN}
DIF_IN differential clock inputs
1.5
5
pF
1
2.7
pF
1,6
C_OUT
Output pin capacitance
6
pF
1
Clk Stabilization
T_STAB
From V_DD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
0.6
1
ms
1,2
Input SS Modulation
Frequency
f_MODIN
Allowable Frequency
(Triangular Modulation)
30
31.500
33
kHz
1
OE# Latency
t_LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
1
3
clocks 1,3
Tdrive_PD#
t_DRVPD
DIF output enable after
PD# de-assertion
300
us
1,3
Tfall
t_F
Fall time of single-ended control inputs
5
ns
1,2
Trise
t_R
Rise time of single-ended control inputs
5
ns
1,2
SMBus Input Low Voltage V_ILSMB
V_DDSMB = 3.3V, see note 4 for V_DDSMB < 3.3V
0.8
V
1, 4
SMBus Input High Voltage V_IHSMB
V_DDSMB = 3.3V, see note 5 for V_DDSMB < 3.3V
2.1
3.6
V
1, 5
SMBus Output Low Voltage V_OLSMB
@ I_PULLUP
0.4
V
1
SMBus Sink Current
I_PULLUP
@ V_OL
4
mA
1
Nominal Bus Voltage
V_DDSMB
1.7
3.6
V
1
SCLK/SDATA Rise Time
t_RSMB
(Max VIL - 0.15) to (Min VIH + 0.15)
1000
ns
1
SCLK/SDATA Fall Time
SMBus Operating
Frequency
t_FSMB
f_MAXSMB
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
300
ns
1
400
kHz 1,7
1_{Guaranteed by design and characterization, not 100% tested in production.}
2_{Control input must be monotonic from 20% to 80% of input swing.}
3_{Time from deassertion until outputs are >200 mV}
4 _{For VDDSMB < 3.3V, VILSMB <= 0.35VDDSMB}
5 _{For VDDSMB < 3.3V, VIHSMB >= 0.65VDDSMB}
6_{DIF_IN input}
7_{The differential input clock must be running for the SMBus to be active}
REVISION E 04/28/16
7
4 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHM