9DBV0441 Datasheet, PDF (6/17 Pages) Integrated Circuit Systems – 53mW typical power consumption in PLL mode

9DBV0441 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBV0441. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
Supply Voltage
VDDx
Applies to all VDD pins
Input Voltage
V_IN
Input High Voltage, SMBus V_IHSMB
Storage Temperature
Ts
SMBus clock and data pins
Junction Temperature
Tj
Input ESD protection
ESD prot
Human Body Model
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Operation under these conditions is neither implied nor guaranteed.}
3 _{Not to exceed 2.5V.}
MIN
-0.5
-0.5
-65
2000
TYP
MAX
2.5
V_DD+0.5V
3.6V
150
125
UNITS
V
V
V
°C
°C
V
NOTES
1,2
1, 3
1
1
1
1
Electrical Characteristics–Clock Input Parameters
TA = T_COM or T_IND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Input High Voltage - DIF_IN V_IHDIF
Input Low Voltage - DIF_IN
Input Common Mode
Voltage - DIF_IN
V_ILDIF
V_COM
Differential inputs
(single-ended measurement)
Differential inputs
(single-ended measurement)
Common Mode Input Voltage
600
800
V_SS - 300
0
300
1150
mV
1
300
mV 1,3
725
mV
1
Input Amplitude - DIF_IN V_SWING
Peak to Peak value (V_IHDIF - V_ILDIF)
300
Input Slew Rate - DIF_IN dv/dt
Measured differentially
0.4
1450
mV
1
V/ns 1,2
Input Leakage Current
I_IN
V_IN = V_{DD ,} V_IN = GND
-5
Input Duty Cycle
d_tin
Measurement from differential wavefrom
45
Input Jitter - Cycle to Cycle J_DIFIn
Differential Measurement
0
1 _{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Slew rate measured through +/-75mV window centered around differential zero}
5
uA
1
55
%
1
150
ps
1
3 _{The device can be driven from a single ended clock by driving the true clock and biasing the complement clock input to the VBIAS, where VBIAS}
is (V_IHHIGH - V_IHLOW)/2
4 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHM
6
REVISION E 04/28/16