9DBV0441 Datasheet, PDF (3/17 Pages) Integrated Circuit Systems – 53mW typical power consumption in PLL mode

Power Connections
Pin Number
VDD
GND
4
7
9
8
16, 25
15,20,26,30
21
20
Description
Input receiver analog
Digital Power
DIF outputs
PLL Analog
Frequency Select Table
FSEL
Byte3 [4:3]
00 (Default)
01
10
11
CLK_IN
(MHz)
100.00
50.00
125.00
Reserved
DIFx
(MHz)
CLK_IN
CLK_IN
CLK_IN
Reserved
PLL Operating Mode
HiBW_BypM_LoBW#
0
M
1
MODE
PLL Lo BW
Bypass
PLL Hi BW
Byte1 [7:6]
Readback
00
01
11
Byte1 [4:3]
Control
00
01
11
9DBV0441 DATASHEET
REVISION E 04/28/16
3
4 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHM