9DBV0441 Datasheet, PDF (2/17 Pages) Integrated Circuit Systems – 53mW typical power consumption in PLL mode

9DBV0441 DATASHEET
Pin Configuration
^vHIBW_BYPM_LOBW# 1
FB_DNC 2
FB_DNC# 3
VDDR1.8 4
CLK_IN 5
CLK_IN# 6
GNDR 7
GNDDIG ₈
32 31 30 29 28 27 26 25
24 vOE2#
23 DIF2#
22 DIF2
9DBV0441 21 VDDA1.8
20 GNDA
19 DIF1#
18 DIF1
17 vOE1#
9 10 11 12 13 14 15 16
32-pin VFQFPN, 5x5 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
^v prefix indicates internal 120KOhm pull up AND pull down resistor (biased to
VDD/2)
v prefix indicates internal 120KOhm pull down resistor
SMBus Address Selection Table
State of SADR on first application of
CKPWRGD_PD#
SADR
0
M
1
Address
1101011
1101100
1101101
+ Read/Write bit
x
x
x
Power Management Table
CKPWRGD_PD#
CLK_IN
SMBus
OEx bit
OEx# Pin
DIFx
PLL
True O/P Comp. O/P
0
X
X
X
Low
Low
Off
1
Running
0
X
Low
Low
On¹
1
Running
1
0
Running
Running
On¹
1
Running
1
1
Low
Low
On¹
1. If Bypass mode is selected, the PLL will be off, and outputs will be running.
4 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHM
2
REVISION E 04/28/16