9DBV0441 Datasheet, PDF (4/17 Pages) Integrated Circuit Systems – 53mW typical power consumption in PLL mode

9DBV0441 DATASHEET
Pin Descriptions
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Pin Name
^vHIBW_BYPM_LOBW#
FB_DNC
FB_DNC#
VDDR1.8
CLK_IN
CLK_IN#
GNDR
GNDDIG
VDDDIG1.8
SCLK_3.3
SDATA_3.3
vOE0#
DIF0
DIF0#
GND
VDDO1.8
vOE1#
DIF1
DIF1#
GNDA
VDDA1.8
DIF2
DIF2#
vOE2#
VDDO1.8
GND
DIF3
DIF3#
vOE3#
GND
^CKPWRGD_PD#
Type Pin Description
LATCHED IN
Trilevel input to select High BW, Bypass or Low
See PLL Operating Mode Table for Details.
BW mode.
DNC
True clock of differential feedback. The feedback output and feedback input are
connected internally on this pin. Do not connect anything to this pin.
DNC
Complement clock of differential feedback. The feedback output and feedback
input are connected internally on this pin. Do not connect anything to this pin.
PWR
1.8V power for differential input clock (receiver). This VDD should be treated as
an Analog power rail and filtered appropriately.
IN
True Input for differential reference clock.
IN
Complementary Input for differential reference clock.
GND Analog Ground pin for the differential input (receiver)
GND Ground pin for digital circuitry
PWR 1.8V digital power (dirty power)
IN
Clock pin of SMBus circuitry, 3.3V tolerant.
I/O
Data pin for SMBus circuitry, 3.3V tolerant.
IN
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
GND Ground pin.
PWR Power supply for outputs, nominally 1.8V.
IN
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
GND Ground pin for the PLL core.
PWR 1.8V power for the PLL core.
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
PWR Power supply for outputs, nominally 1.8V.
GND Ground pin.
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
GND Ground pin.
Input notifies device to sample latched inputs and start up on first high assertion.
IN
Low enters Power Down Mode, subsequent high assertions exit Power Down
Mode. This pin has internal pull-up resistor.
32 ^SADR_tri
LATCHED IN Tri-level latch to select SMBus Address. See SMBus Address Selection Table.
4 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHM
4
REVISION E 04/28/16