ICS8305I Datasheet, PDF (6/16 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER

ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 5B. AC CHARACTERISTICS, V_DD = 3.3V ± 5%, V_DDO = 2.5V ± 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f_MAX
Output Frequency
Ref = CLK/nCLK
Ref = LVCMOS_CLK
350
MHz
300
MHz
LVCMOS_CLK;
tp_LH
Propagation Delay, NOTE 1A
Low to High
CLK, nCLK;
1.75
NOTE 1B
tsk(o) Output Skew; NOTE 2, 6
Measured on the Rising Edge
2.95
ns
40
ps
tsk(pp) Part-to-Part Skew; NOTE 3, 6
800
ps
Buffer Additive Phase Jitter, RMS;
tjit
refer to Additive Phase Jitter section,
NOTE 5
0.04
ps
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
100
IJ 166MHz
45
f > 166MHz
42
700
ps
55
%
58
%
t_EN
Output Enable Time; NOTE 4
5
ns
t_DIS
Output Disable Time; NOTE 4
5
ns
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE 1A: Measured from the V_DD/2 of the input to V_DDO/2 of the output.
NOTE 1B: Measured from the differential input crossing point to V_DDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V_DDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: Driving only one input clock.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5C. AC CHARACTERISTICS, V_DD = 3.3V ± 5%, V_DDO = 1.8V ± -0.15V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
f_MAX
Output Frequency
Ref = CLK/nCLK
Ref = LVCMOS_CLK
LVCMOS_CLK;
tp_LH
Propagation Delay, NOTE 1A
Low to High
CLK, nCLK;
1.75
NOTE 1B
tsk(o) Output Skew; NOTE 2, 6
Measured on the Rising Edge
tsk(pp)
tjit
Part-to-Part Skew; NOTE 3, 6
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 5
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
100
IJ 166MHz
45
f > 166MHz
42
t_EN
Output Enable Time; NOTE 4
t_DIS
Output Disable Time; NOTE 4
For notes, see Table 5B.
8305AGI
www.idt.com
Typical
Maximum
350
300
Units
MHz
MHz
3.7
ns
45
ps
900
ps
0.04
ps
700
ps
55
%
58
%
5
ns
5
ns
REV. B SEPTEMBER 17, 2012
6