ICS8305I Datasheet, PDF(10/16 Page) Integrated Circuit Systems – LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER

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ICS8305I Datasheet, PDF (10/16 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER

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ICS8305I

LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/

LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER

APPLICATION INFORMATION

RECOMMENDATION FOR UNUSED INPUT AND OUTPUT PINS

Inputs:

Outputs:

LVCMOS_CLK Input

For applications not requiring the use of a clock input, it can

be left floating. Though not required, but for additional protec-

tion, a 1kÎ© resistor can be tied from the LVCMOS_CLK input

to ground.

LVCMOS Outputs

All unused LVCMOS outputs can be left floating. There should

be no trace attached.

CLK/nCLK Inputs

For applications not requiring the use of the differential input,

both CLK and nCLK can be left floating. Though not required,

but for additional protection, a 1kÎ© resistor can be tied from

CLK to ground.

LVCMOS Control Pins

All control pins have internal pull-ups or pull-downs; addi-

tional resistance is not required but can be added for addi-

tional protection. A 1kÎ© resistor can be used.

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

Figure 2 shows how a differential input can be wired to accept single ended

levels. The reference voltage V1= VDD/2 is generated by the bias resistors R1

and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias.

This bias circuit should be located as close to the input pin as possible. The ratio

of R1 and R2 might need to be adjusted to position the V1in the center of the

input voltage swing. For example, if the input clock swing is 2.5V and

V = 3.3V, R1 and R2 value should be adjusted to set V at 1.25V.The values

below are for when both the single ended swing and V are at the same voltage.

This configuration requires that the sum of the output impedance of the driver

(Ro) and the series resistance (Rs) equals the transmission line impedance. In

addition, matched termination at the input will attenuate the signal in half. This

can be done in one of two ways. First, R3 and R4 in parallel should equal the

slower and weaker LVCMOS driver. When using single-ended signaling, the

noise rejection benefits of differential signaling are reduced. Even though the

differential input can handle full rail LVCMOS signaling, it is recommended that

the amplitude be reduced. The datasheet specifies a lower differential ampli-

tude, however this only applies to differential signals. For single-ended applica-

tions, the swing can be larger, however VIL cannot be less than -0.3V and VIH

cannot be more than VDD + 0.3V. Though some of the recommended compo-

nents might not be used, the pads should be placed in the layout. They can be

utilized for debugging purposes. The datasheet specifications are characterized

and guaranteed by using a differential signal.

8305AGI

FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

www.idt.com

REV. B SEPTEMBER 17, 2012

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