ICS8305I Datasheet, PDF (2/16 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER

ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 9, 13
GND
Power
Power supply ground.
2
OE
Input
Pullup
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
3
V_DD
Power
Core supply pin.
Synchronizing clock enable. When LOW, the output clocks are
4
CLK_EN
Input Pullup disabled. When HIGH, output clocks are enabled.
LVCMOS / LVTTL interface levels.
5
CLK
Input Pulldown Non-inverting differential clock input.
6
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input. V_DD/2 default when left floating.
Clock select input. When HIGH, selects CLK, nCLK inputs.
7
CLK_SEL
Input Pullup When LOW, selects LVCMOS_CLK input.
LVCMOS / LVTTL interface levels.
8
LVCMOS_CLK Input Pulldown LVCMOS / LVTTL clock input.
10, 12, 14, 16 Q3, Q2, Q1, Q0 Output
Clock outputs. LVCMOS / LVTTL interface levels.
11, 15
V_DDO
Power
Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C
IN
R_PULLUP
R_PULLDOWN
C_PD
R_OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
11
pF
5
7
12
Ω
8305AGI
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2
REV. B SEPTEMBER 17, 2012