ICS8305I Datasheet, PDF (1/16 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER

ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS8305I is a low skew, 1-to-4, Differential/LVCMOS-to-
LVCMOS/LVTTL Fanout Buffer. The ICS8305I has selectable
clock inputs that accept either differential or single ended
input levels. The clock enable is internally synchronized to
eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin. Outputs are
forced LOW when the clock is disabled. A separate output
enable pin controls whether the outputs are in the active or
high impedance state.
Guaranteed output and part-to-part skew characteristics make
the ICS8305I ideal for those applications demanding well de-
fined performance and repeatability.
FEATURES
• 4 LVCMOS/LVTTL outputs
• Selectable differential or LVCMOS/LVTTL clock inputs
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• LVCMOS_CLK supports the following input types:
LVCMOS, LVTTL
• Maximum output frequency: 350MHz
• Output skew: 40ps (maximum)
• Part-to-part skew: 700ps (maximum)
• Additive phase jitter, RMS: 0.04ps (typical)
• 3.3V core, 3.3V, 2.5V or 1.8V output operating supply
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
CLK_EN
LVCMOS_CLK
00
CLK
nCLK
1¹
CLK_SEL
D
Q
LE
OE
PIN ASSIGNMENT
GND 1 16 Q0
OE 2
1 5 VDDO
VDD 3
14 Q1
CLK_EN 4 13 GND
CLK 5 12 Q2
Q0
nCLK 6
1 1 VDDO
CLK_SEL 7 10 Q3
Q1
LVCMOS_CLK 8
9 GND
Q2
ICS8305I
16-Lead TSSOP
4.4mm x 3.0mm x 0.92mm package body
Q3
G Package
Top View
8305AGI
www.idt.com
1
REV. B SEPTEMBER 17, 2012