ICS8305I Datasheet, PDF (5/16 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER

ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V_DD = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
nCLK
I_IH
Input High Current
CLK
V_IN = V_DD = 3.465V
V_IN = V_DD = 3.465V
nCLK
I_IL
Input Low Current
CLK
V_IN = 0V, V_DD = 3.465V
V = 0V, V = 3.465V
IN
DD
-150
-5
V_PP
V_CMR
Peak-to-Peak Input Voltage
Common Mode Input Voltage;
NOTE 1, 2
0.15
GND + 0.5
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is V_DD + 0.3V.
NOTE 2: Common mode voltage is defined as V_IH.
Maximum
150
150
1.3
V_DD - 0.85
Units
µA
µA
µA
µA
V
V
TABLE 5A. AC CHARACTERISTICS, V_DD = V_DDO = 3.3V ± 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f_MAX
Output Frequency
Ref = CLK/nCLK
Ref = LVCMOS_CLK
LVCMOS_CLK;
tp_LH
Propagation Delay, NOTE 1A
Low to High
CLK, nCLK;
1.75
NOTE 1B
tsk(o) Output Skew; NOTE 2, 6
Measured on the Rising Edge
350
MHz
300
MHz
2.8
ns
40
ps
tsk(pp)
tjit
t_R / t_F
odc
Part-to-Part Skew; NOTE 3, 6
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 5
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
IJ 200MHz
ƒ> 200MHz
700
ps
0.04
ps
100
700
ps
45
55
%
42
58
%
t_EN
Output Enable Time; NOTE 4
5
ns
t_DIS
Output Disable Time; NOTE 4
5
ns
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE 1A: Measured from the V_DD/2 of the input to V_DDO/2 of the output.
NOTE 1B: Measured from the differential input crossing point to V_DDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V_DDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V_DDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: Driving only one input clock.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
8305AGI
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REV. B SEPTEMBER 17, 2012