ICS8305I Datasheet, PDF (4/16 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER

ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V_DD
Inputs, V_I
Outputs, V_O
Package Thermal Impedance, θ_JA
Storage Temperature, T_STG
4.6V
-0.5V to V_DD + 0.5 V
-0.5V to V_DDO + 0.5V
89°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V_DD = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
V_DD
Core Supply Voltage
3.135
3.135
V_DDO
Output Supply Voltage
2.375
1.65
I_DD
Power Supply Current
I_DDO
Output Supply Current
Typical
3.3
3.3
2.5
1.8
Maximum
3.465
3.465
2.625
1.95
21
5
Units
V
V
V
V
mA
mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, V_DD = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
V_IH
Input
CLK_EN, CLK_SEL, OE
High Voltage _{LVCMOS_CLK}
V_IL
Input
CLK_EN, CLK_SEL, OE
Low Voltage _{LVCMOS_CLK}
2
V_DD + 0.3
V
2
V_DD + 0.3
V
-0.3
0.8
V
-0.3
1.3
V
I_IH
Input
CLK_EN, CLK_SEL, OE
High Current _{LVCMOS_CLK}
V_DD = V_IN = 3.465V
V_DD = V_IN = 3.465V
5
µA
150
µA
I_IL
Input
CLK_EN, CLK_SEL, OE
Low Current _{LVCMOS_CLK}
V_DD = 3.465V, V_IN = 0V
V_DD = 3.465V, V_IN = 0V
-150
-5
µA
µA
V_DDO = 3.3V ± 5%
2.6
V
V_OH
Output High Voltage; NOTE 1
V_DDO = 2.5V ± 5%
1.8
V
V_DDO = 1.8V ± 0.15V
V_DDO - 0.3
V
V_DDO = 3.3V ± 5%
0.5
V
V_OL
Output Low Voltage; NOTE 1
V_DDO = 2.5V ± 5%
0.5
V
V_DDO = 1.8V ± 0.15V
0.4
V
I_OZL
Output Tristate Current Low
-5
µA
I_OZH
Output Tristate Current High
5
µA
NOTE 1: Outputs terminated with 50Ω to V_DDO/2. See Parameter Measurement Information, Output Load Test Circuit.
8305AGI
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REV. B SEPTEMBER 17, 2012