ICS9DS400 Datasheet, PDF (5/19 Pages) Integrated Device Technology – Four Output Differential Buffer for PCIe Gen 2 with Spread

ICS9DS400
Four Output Differential Buffer for PCIe for Gen 2 with Spread
Advance Information
Absolute Max
Symbol
Parameter
VDD
3.3V Supply Voltage
V_IL
Input Low Voltage
V_IH
Input High Voltage
Ts
Storage Temperature
Tcase
Case Temperature
Input ESD protection
ESD prot
human body model
Min
GND-0.5
-65
2000
Max
4.6
V_DD+0.5V
150
115
Units
V
V
V
°_C
°C
V
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A =Over the Specified Operating Range; V_DD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Input High Voltage
V_IH
Input Low Voltage
V_IL
Input High Current
I_IH
3.3 V +/-5%
3.3 V +/-5%
V_IN = V_DD
2
GND - 0.3
-5
Input Low Current
I_IL1
V_IN = 0 V; Inputs with no pull-up resistors
-5
I_IL2
V_IN = 0 V; Inputs with pull-up resistors
-200
Operating Supply Current I_DD3.3OP
Full Active, C_L = Full load;
Powerdown Current
I_DD3.3PD
all diff pairs driven
all differential pairs tri-stated
Input Frequency
F_iPLL
PCIe Mode (Bypass#/PLL= 1)
90
F_iBYPASS
Bypass Mode ((Bypass#/PLL= 0)
33
Pin Inductance
L_pin
C_IN
Logic Inputs, except SRC_IN
1.5
Capacitance
C_{INSRC_IN}
SRC_IN differential clock inputs
1.5
C_OUT
Output pin capacitance
Clk Stabilization
T_STAB
From V_DD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st
clock
SS Modulation
Frequency
f_MOD
Assuming 100 MHz input
(Triangular Modulation)
30
OE# Latency
t_LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
1
Tdrive_PD#
t_DRVPD
DIF output enable after
PD# de-assertion
Tfall
t_F
Fall time of PD# and SRC_STOP#
Trise
t_R
Rise time of PD# and SRC_STOP#
SMBus Voltage
V_MAX
Maximum input voltage
Low-level Output Voltage V_OL
@ I_PULLUP
Current sinking at V_OL
I_PULLUP
4
SCLK/SDATA
Clock/Data Rise Time
t_RSMB
(Max VIL - 0.15) to
(Min VIH + 0.15)
SCLK/SDATA
Clock/Data Fall Time
t_FSMB
(Min VIH + 0.15) to
(Max VIL - 0.15)
SMBus Operating
Frequency
f_MAXSMB Maximum SMBus operating frequency
1_{Guaranteed by design and characterization, not 100% tested in production.}
2_{See timing diagrams for timing requirements.}
3_{Time from deassertion until outputs are >200 mV}
4_{SRC_IN input}
5_{The differential input clock must be running for the SMBus to be active}
IDT^TM/ICS^TM Four Output Differential Buffer for PCIe Gen 2 with Spread
100.00
32.000
MAX
V_DD + 0.3
0.8
5
UNITS NOTES
V
1
V
1
uA
1
uA
1
uA
1
125
mA
1
30
mA
1
6
mA
1
110
MHz
1
400
MHz
1
7
nH
1
5
pF
1
2.7
pF
1,4
6
pF
1
1
ms
1,2
33
kHz
1
3
cycles 1,3
300
5
5
5.5
0.4
1000
us
1,3
ns
1
ns
2
V
1
V
1
mA
1
ns
1
300
ns
1
100
kHz 1,5
1626 09/17/09
5