ICS9DS400 Datasheet, PDF (15/19 Pages) Integrated Device Technology – Four Output Differential Buffer for PCIe Gen 2 with Spread

ICS9DS400
Four Output Differential Buffer for PCIe for Gen 2 with Spread
Advance Information
DIF_STOP#
The DIF_STOP# signal is an active-low asynchronous input that cleanly stops and starts the DIF outputs. A valid clock must
be present on DIF_IN for this input to work properly. The DIF_STOP# signal is de-bounced and must remain stable for two
consecutive rising edges of DIF# to be recognized as a valid assertion or de-assertion.
DIF_STOP# - Assertion
Asserting DIF_STOP# causes all DIF outputs to stop after their next transition (if the control register settings allow the output
to stop). When the DIF_STOP# drive bit is ‘0’, the final state of all stopped DIF outputs is DIF = High and DIF# = Low. There
is no change in output drive current. DIF is driven with 6xIREF. DIF# is not driven, but pulled low by the termination. When the
DIF_STOP# drive bit is ‘1’, the final state of all DIF output pins is Low. Both DIF and DIF# are not driven.
DIF_STOP# - De-assertion (transition from '0' to '1')
All stopped differential outputs resume normal operation in a glitch-free manner. The de-assertion latency to active outputs is
2-6 DIF clock periods, with all DIF outputs resuming simultaneously. If the DIF_STOP# drive control bit is ‘1’ (tri-state), all
stopped DIF outputs must be driven High (>200 mV) within 10 ns of de-assertion.
DIF_STOP_1 (DIF_Stop = Driven, PD = Driven)
1mS
SDRICF_Stop#
PWRDWN#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
DIF_STOP_2 (DIF_Stop =Tristate, PD = Driven)
1mS
SRDCIF_Stop#
PWRDWN#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
IDT^TM/ICS^TM Four Output Differential Buffer for PCIe Gen 2 with Spread
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1626 09/17/09