ICS9DS400 Datasheet, PDF (12/19 Pages) Integrated Device Technology – Four Output Differential Buffer for PCIe Gen 2 with Spread

ICS9DS400
Four Output Differential Buffer for PCIe for Gen 2 with Spread
Advance Information
SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (D8/D9)
Byte 0
Bit 7
Bit 6
Bit 5
Bit 4
Pin #
-
-
-
Name
PD_Mode
STOP_Mode
1
SPREAD_AMT(1)
Bit 3
-
SPREAD_AMT(0)
Control Function
PD# drive mode
SRC_Stop# drive mode
Reserved
Spread % MSB
Spread % LSB
Type
RW
RW
RW
RW
0
1
driven
Hi-Z
driven
Hi-Z
00 = -0.125%
01 = -0.25%
10 = -0.375%
11 = -0.50%
Default
0
0
0
Latch
1
Bit 2
28
Bit 1
22
Bit 0
-
SPREAD_EN
BYPASS#
Byte0 CONTROL
Turns on spread
BYPASS#_SSCG
Selects control source of Byte 0
RW SS Off SS On Latch
RW fan-out SSCG Latch
RW Smbus Input Pins 1
Notes: Pins 1, 22 and 28 are latched into Byte 0 on the first power up of the device. Bits [4:1] will NOT reflect
changes in these pin states after power up, even though the pins are controlling the function of the part. Setting
Byte 0 bit 0 to 0 allows the SMBus to write Bits [4:1] and transfers control of the functions from the pins to SMBus.
Once Byte 0 bit 0 is set to 0, the pins no longer impact Byte 0, bits [4:1] or the device function.
SMBus Table: Output Control Register
Byte 1 Pin #
Name
Control Function
Type
0
1
Bit 7
-
Reserved
Reserved
RW
Reserved
Bit 6 22,23
DIF_6
Output Enable
RW Disable Enable
Bit 5 19,20
DIF_5
Output Enable
RW Disable Enable
Bit 4
-
Reserved
Reserved
RW
Reserved
Bit 3
-
Reserved
Reserved
RW
Reserved
Bit 2
9,10
DIF_2
Output Enable
RW Disable Enable
Bit 1
6,7
DIF_1
Output Enable
RW Disable Enable
Bit 0
-
Reserved
Reserved
RW
Reserved
NOTE: The SMBus Output Enable Bit must be '1' AND the respective OE pin must be active for the output to run!
Default
1
1
1
1
1
1
1
1
SMBus Table: OE Pin Control Register
Byte 2 Pin #
Name
Bit 7
-
Reserved
Bit 6 22,23
DIF_6
Bit 5
-
Reserved
Bit 4
-
Reserved
Bit 3
-
Reserved
Bit 2
-
Reserved
Bit 1
6,7
DIF_1
Bit 0
-
Reserved
Control Function
Reserved
DIF_6 Stoppable with OE6
Reserved
Reserved
Reserved
Reserved
DIF_1 Stoppable with OE1
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
Reserved
0
Free-run Stoppable 0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Free-run Stoppable 0
Reserved
0
SMBus Table: Reserved Register
Byte 3 Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IDT^TM/ICS^TM Four Output Differential Buffer for PCIe Gen 2 with Spread
12
Type
0
1
Default
X
X
X
X
X
X
X
X
1626 09/17/09