ICS9DS400 Datasheet, PDF (3/19 Pages) Integrated Device Technology – Four Output Differential Buffer for PCIe Gen 2 with Spread

ICS9DS400
Four Output Differential Buffer for PCIe for Gen 2 with Spread
Advance Information
Pin Description for OE_INV = 0
PIN #
PIN NAME
PIN
TYPE
1
VDD
2
SRC_IN
3
SRC_IN#
4
GND
5
VDD
6
DIF_1
7
DIF_1#
PWR
IN
IN
PWR
PWR
OUT
OUT
8
OE_1
IN
9
DIF_2
10 DIF_2#
11 VDD
OUT
OUT
PWR
12 BYPASS#_SSCG IN
13 SCLK
IN
14 SDATA
I/O
15 PD#
IN
16 DIF_STOP#
17 SPREAD_EN
18 VDD
19 DIF_5#
20 DIF_5
21 OE_6
22 DIF_6#
23 DIF_6
24 VDD
25 OE_INV
IN
IN
PWR
OUT
OUT
IN
OUT
OUT
PWR
IN
26 IREF
27 GNDA
28 VDDA
OUT
PWR
PWR
INTERNAL
DESCRIPTION
PULL UP
OR PULL
DOWN?
Power supply, nominal 3.3V
N/A
0.7 V Differential SRC TRUE input
N/A
0.7 V Differential SRC COMPLEMENTARY input
N/A
Ground pin.
N/A
Power supply, nominal 3.3V
N/A
0.7V differential true clock output
N/A
0.7V differential Complementary clock output
N/A
Active high input for enabling output 1.
0 = tri-state outputs, 1= enable outputs
PULL UP
0.7V differential true clock output
N/A
0.7V differential Complementary clock output
N/A
Power supply, nominal 3.3V
N/A
Input to select Bypass(fan-out) or SSCG (PLL) mode
0 = Bypass mode, 1= SSCG mode
PULL UP
Clock pin of SMBus circuitry, 5V tolerant.
N/A
Data pin for SMBus circuitry, 3.3V tolerant.
N/A
Asynchronous active low input pin used to power down the device. The
internal clocks are disabled and the VCO and the crystal osc. (if any) are
PULL UP
stopped.
Active low input to stop differential output clocks.
PULL UP
Asynchronous, active high input to enable spread spectrum functionality.
PULL UP
Power supply, nominal 3.3V
N/A
0.7V differential Complementary clock output
N/A
0.7V differential true clock output
N/A
Active high input for enabling output 6.
0 = tri-state outputs, 1= enable outputs
PULL UP
0.7V differential Complementary clock output
N/A
0.7V differential true clock output
N/A
Power supply, nominal 3.3V
N/A
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
N/A
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in order N/A
to establish the appropriate current. 475 ohms is the standard value.
Ground pin for the PLL core.
N/A
3.3V power for the PLL core.
N/A
IDT^TM/ICS^TM Four Output Differential Buffer for PCIe Gen 2 with Spread
3
1626 09/17/09