ICS9DS400 Datasheet, PDF (1/19 Pages) Integrated Device Technology – Four Output Differential Buffer for PCIe Gen 2 with Spread

Advance Information
Four Output Differential Buffer for PCIe Gen 2 with Spread
ICS9DS400
General Description
The 9DS400 is pin compatible to the 9DB403, but adds the
ability to inject spread spectrum onto the incoming differential
clock, while maintaining good phase noise.
Recommended Application
DB400 where spread spectrum needs to be added to the
incoming clock.
Key Specifications
• Output cycle-cycle jitter < 50ps
• Output to Output skew <50ps
• Phase jitter: PCIe Gen1 < 86ps peak to peak
• Phase jitter: PCIe Gen2 < 3.0/3.1ps rms
Features/Benefits
• Bypass mode
• Supports undriven differential outputs in PD# and
SRC_STOP# modes for power management.
Output Features
• 4 - 0.7V current-mode differential output pairs.
• Supports Spread Injection mode and fanout mode.
• Two pin selectable down spread amounts: 0.5% and
0.25%.
• 50-110 MHz operation in PLL mode
• 50-400 MHz operation in Bypass mode
Functional Block Diagram
2
OE(6,1)#
SRC_IN
SRC_IN#
Spread
Generating
PLL
DIF_STOP
SPREAD_EN
BYPASS#_SSCG
PD
SDATA
SCLK
CONTROL
LOGIC
M
U
X
STOP
4
LOGIC
DIF(6,5,2,1))
IREF
Polarities shown assuming that OE_INV = 1
IDT^TM/ICS^TM Four Output Differential Buffer for PCIe Gen 2 with Spread
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1626 09/17/09