ICS1894-40 Datasheet, PDF (5/52 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Strapping Options
Pin
Number
1
Pin
Name
AMDIX
16
HWSW/CRS
17
REGPIN/COL
18
AMDIX/RXD2
38
P4/LED2
19
P3/RXD2
12
P2/INT
40
P1/LED1
39
P0/LED0
21
SI/LED4
20
RXTRI/RXD1
22
FDPX/RXD0
23
RMII/RXDV
24
SPEED
26 ANSEL/RXCLK
27
NOD/RXER
28 SPEED/TXCLK
32
LED3
Pin
Type¹
Pin Function
IN/Ipu 1 = AMDIX enable
0 = AMDIX disable
IO/Ipd Hardware pin select enable. Active during power-on and hardware reset.
IO/Ipd Full register access enable. Active during power-on and hardware reset.
IO/Ipu 1 = AMDIX enable
0 = AMDIX disable
IO/Ipu The PHY address is set by P[4:0] at power-on reset. P0 and P1 must have external
IO/Ipd ^{pull-up or pull-down to set address at start up.}
IO/Ipd
IO/
IO/
IO/Ipd MII/SI mode select. Active during power-on and hardware reset.
IO/Ipd 1=RX tri-state for MII/RMII interface
0=RX output enable
IO/Ipu 1=Full duplex
0=Half duplex
Ignored if Auto negotiation is enabled
IO/Ipd [1x]=RMII mode
[01]=SI mode (Serial interface mode)
[00]=MII mode
IO/Ipu 1=100M mode
0=10M mode
IO/Ipu 1=Enable auto negotiation
0=Disable auto negotiation
IO/Ipd 0=Node mode
1=repeater mode
IO/Ipu 1=100M mode
0=10M mode
Ignored if Auto negotiation is enabled
IO/Ipu LED3 output
1. Ipu/O = Input with internal pull-up during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down during power-up/reset; output pin otherwise.
Functional Description
The ICS1894-32 is a stream processor. During data
transmission, it accepts sequential nibbles from its MAC
(Media Access Control) converts them into a serial bit
stream, encodes them, and transmits them over the medium
through an external isolation transformer. When receiving
data, the ICS1894-32 converts and decodes a serial bit
stream (acquired from an isolation transformer that
interfaces with the medium) into sequential nibbles. It
subsequently presents these nibbles to its MAC Interface.
The ICS1894-32 implements the OSI model’s physical
layer, consisting of the following, as defined by the ISO/IEC
8802-3 standard:
• Physical Coding sublayer (PCS)
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 5
ICS1894-40 REV C 092909