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ICS1894-40 Datasheet, PDF (43/52 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE | |||
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ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
100M Media Independent Interface: Input-to-Carrier Assertion/De-Assertion
The table below lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The time
periods consist of timings of signals on the following pins:
⢠TP_RX (that is, TP_RXP and TP_RXN)
⢠CRS
⢠COL
The 100M MDI Input to Carrier Assertion/De-Assertion Timing Diagram shows the timing diagram for the time
periods.
Time
Period
Parameter
Conditions Min. Typ. Max. Units
t1 First Bit of /J/ into TP_RX to CRS Assert â
â
10 â 14 Bit times
t2 First Bit of /J/ into TP_RX while
Transmitting Data to COL Assert â
Half-Duplex Mode 9
â 13 Bit times
t3 First Bit of /T/ into TP_RX to CRS
De-Assert â¡
â
13 â 18 Bit times
t4 First Bit of /T/ Received into TP_RX to
COL De-Assert â¡
Half-Duplex Mode 13 â 18 Bit times
â The IEEE maximum is 20 bit times.
â¡The IEEE minimum is 13 bit times, and the maximum is 24 bit times.
100M MDI Input to Carrier Assertion/De-Assertion Timing Diagram
First bit
First bit of /T/
TP_RXâ
t3
t1
CRS
COL
t2
t4
â Shown
unscrambled.
IDT⢠/ ICS⢠10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 43
ICS1894-40 REV C 092909
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