ICS1894-40 Datasheet, PDF (4/52 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Pin
Number
28
29
30
31
32
33
34
35
36
37
38
Pin
Name
SPEED/
TXCLK
TXEN
TXD0
VDDD
LED3
TXD1
TXT2
TXD3
REF_OUT
REF_IN
P4/LED2
39
P0/LED0
40
P1/LED1
Pin
Type
Pin Description
IO/Ipu 10M/100M select as input (during power on reset and hardware reset)
Transmit clock for MII as output
Input Transmit enable for both RMII and MII
Input Transmit data Bit 0 for both RMII and MII
Power Core Power Supply
IO/Ipd LED3 output
Input Transmit data Bit 1for both RMII and MII
Input Transmit data Bit 2 for MII
Input Transmit data Bit 3 for MII
Output 25 MHz crystal output
Input 25 MHz crystal (or clock) input for MII. 50MHz clock input for RMII
IO/Ipu PHY address Bit 4 as input (during power on reset and hardware reset)
And LED # 2 as output
IO PHY address Bit 0 as input (during power on reset and hardware reset) and LED #
0(function configurable, default is "activity/no activity") as output
IO PHY address Bit 1 as input (during power on reset and hardware reset) and LED #
1 (function configurable, default is "10/100 mode") as output
Notes:
1. Ipd = Input with internal pull-down.
Ipu = Input with internal pull-up.
Opu = Output with internal pull-up.
Ipu/O = Input with internal pull-up during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down during power-up/reset; output pin otherwise.
2. MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents
valid data to MAC through the MII. RXD[3..0] is invalid when RXDV is de-asserted.
3. RMII Rx Mode: The RXD[1:0] bits are synchronous with REF_CLK. For each clock period in which CRS_DV is
asserted, two bits of recovered data are sent from the PHY.
4. MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid
data from the MAC through the MII. TXD[3..0] has no effect when TXEN is de-asserted.
5. RMII Tx Mode: The TXD[1:0] bits are synchronous with REF_CLK. For each clock period in which TX_EN is
asserted, two bits of data are received by the PHY from the MAC.
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 4
ICS1894-40 REV C 092909