ICS1894-40 Datasheet, PDF (27/52 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Bit
25.9:7
Definition
TX10BIAS_SET
25.6:4
TX100BIAS_SET
25.3:2
OUTDLY_CTL
25.1:0
RX_SET
Register 26-31h - Reserved
When Bit = 0
When Bit = 1
The normal output current of Bias block for 10BaseT
is 540uA. Change the register can modify the current
with a step about 5%
000: output 80% current
001: output 85% current
010: output 90% current
011: output 95% current
100: output 100% current
101: output 105% current
110: output 110% current
111: output 115% current
The normal output current of Bias block for
100BaseTX is 180uA. Change the register can
modify the current with a step about 5%
000: output 80% current
001: output 85% current
010: output 90% current
011: output 95% current
100: output 100% current
101: output 105% current
110: output 110% current
111: output 115% current
This register setting the delay time of digital control
signal for xmit_dac. Increase the setting value can
short the delay time.
00: the longest delay time (same as original design)
01: the long delay time
10: the short delay time
11: the shortest delay time
The output current of Bias block for RX block is
108uA. The register can change the current with a
step about 16.5%
00: output 83.5% current
01: output 100% current
10: output 116.5% current
11: output 133% current
Change this value may modify the RX block
performance.
Ac-
cess
RW
RW
RW
RW
SF De- Hex
fault
4
4
0
1
Note: 1 Ignored if Auto negotiation is enable
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 27
ICS1894-40 REV C 092909