ICS1894-40 Datasheet, PDF (36/52 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
MII Management Interface Timing
The table below lists the significant time periods for the MII Management Interface timing (which consists of timings
of signals on the MDC and MDIO pins). The MII Management Interface Timing Diagram figure shows the timing
diagram for the time periods.
Time
Period
Parameter
t1 MDC Minimum High Time
t2 MDC Minimum Low Time
t3 MDC Period
t4 MDC Rise Time to MDIO Valid
t5 MDIO Setup Time to MDC
t6 MDIO Hold Time after MDC
Conditions Min. Typ. Max. Units
–
160 –
–
ns
–
160 –
–
ns
–
400† †
–
ns
–
0
– 300 ns
–
10
–
–
ns
–
10
–
–
ns
†The ICS1894-40 is tested at 25 MHz (a 40ns period) with a 50pF load. Designs must account for all board loading
of MDC.
MII Management Interface Timing Diagram
MDC
MDIO
(Output)
t1
t2
t3
t4
MDC
MDIO
(Input)
t5
t6
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 36
ICS1894-40 REV C 092909